2 * Keystone2: Common SoC definitions, structures etc.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ASM_ARCH_HARDWARE_H
10 #define __ASM_ARCH_HARDWARE_H
16 #include <linux/sizes.h>
19 #define REG(addr) (*(volatile unsigned int *)(addr))
20 #define REG_P(addr) ((volatile unsigned int *)(addr))
22 typedef volatile unsigned int dv_reg;
23 typedef volatile unsigned int *dv_reg_p;
27 #define KS2_DDRPHY_PIR_OFFSET 0x04
28 #define KS2_DDRPHY_PGCR0_OFFSET 0x08
29 #define KS2_DDRPHY_PGCR1_OFFSET 0x0C
30 #define KS2_DDRPHY_PGSR0_OFFSET 0x10
31 #define KS2_DDRPHY_PGSR1_OFFSET 0x14
32 #define KS2_DDRPHY_PLLCR_OFFSET 0x18
33 #define KS2_DDRPHY_PTR0_OFFSET 0x1C
34 #define KS2_DDRPHY_PTR1_OFFSET 0x20
35 #define KS2_DDRPHY_PTR2_OFFSET 0x24
36 #define KS2_DDRPHY_PTR3_OFFSET 0x28
37 #define KS2_DDRPHY_PTR4_OFFSET 0x2C
38 #define KS2_DDRPHY_DCR_OFFSET 0x44
40 #define KS2_DDRPHY_DTPR0_OFFSET 0x48
41 #define KS2_DDRPHY_DTPR1_OFFSET 0x4C
42 #define KS2_DDRPHY_DTPR2_OFFSET 0x50
44 #define KS2_DDRPHY_MR0_OFFSET 0x54
45 #define KS2_DDRPHY_MR1_OFFSET 0x58
46 #define KS2_DDRPHY_MR2_OFFSET 0x5C
47 #define KS2_DDRPHY_DTCR_OFFSET 0x68
48 #define KS2_DDRPHY_PGCR2_OFFSET 0x8C
50 #define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
51 #define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
52 #define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
53 #define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
55 #define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
57 #define IODDRM_MASK 0x00000180
58 #define ZCKSEL_MASK 0x01800000
59 #define CL_MASK 0x00000072
60 #define WR_MASK 0x00000E00
61 #define BL_MASK 0x00000003
62 #define RRMODE_MASK 0x00040000
63 #define UDIMM_MASK 0x20000000
64 #define BYTEMASK_MASK 0x0003FC00
65 #define MPRDQ_MASK 0x00000080
66 #define PDQ_MASK 0x00000070
67 #define NOSRA_MASK 0x08000000
68 #define ECC_MASK 0x00000001
70 /* DDR3 definitions */
71 #define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
72 #define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
73 #define KS2_DDR3A_DDRPHYC 0x02329000
75 #define KS2_DDR3_MIDR_OFFSET 0x00
76 #define KS2_DDR3_STATUS_OFFSET 0x04
77 #define KS2_DDR3_SDCFG_OFFSET 0x08
78 #define KS2_DDR3_SDRFC_OFFSET 0x10
79 #define KS2_DDR3_SDTIM1_OFFSET 0x18
80 #define KS2_DDR3_SDTIM2_OFFSET 0x1C
81 #define KS2_DDR3_SDTIM3_OFFSET 0x20
82 #define KS2_DDR3_SDTIM4_OFFSET 0x28
83 #define KS2_DDR3_PMCTL_OFFSET 0x38
84 #define KS2_DDR3_ZQCFG_OFFSET 0xC8
86 #define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
89 #define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC
90 #define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4
91 #define KS2_DDR3_ECC_CTRL_OFFSET 0x110
92 #define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114
93 #define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130
94 #define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C
96 /* DDR3 ECC Interrupt Status register */
97 #define KS2_DDR3_1B_ECC_ERR_SYS BIT(5)
98 #define KS2_DDR3_2B_ECC_ERR_SYS BIT(4)
99 #define KS2_DDR3_WR_ECC_ERR_SYS BIT(3)
101 /* DDR3 ECC Control register */
102 #define KS2_DDR3_ECC_EN BIT(31)
103 #define KS2_DDR3_ECC_ADDR_RNG_PROT BIT(30)
104 #define KS2_DDR3_ECC_VERIFY_EN BIT(29)
105 #define KS2_DDR3_ECC_RMW_EN BIT(28)
106 #define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0)
108 #define KS2_DDR3_ECC_ENABLE (KS2_DDR3_ECC_EN | \
109 KS2_DDR3_ECC_ADDR_RNG_PROT | \
110 KS2_DDR3_ECC_VERIFY_EN)
113 #define KS2_EDMA0_BASE 0x02700000
115 /* EDMA3 register offsets */
116 #define KS2_EDMA_QCHMAP0 0x0200
117 #define KS2_EDMA_IPR 0x1068
118 #define KS2_EDMA_ICR 0x1070
119 #define KS2_EDMA_QEECR 0x1088
120 #define KS2_EDMA_QEESR 0x108c
121 #define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x))
124 #define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
125 #define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
127 /* Chip Interrupt Controller */
128 #define KS2_CIC2_BASE 0x02608000
130 /* Chip Interrupt Controller register offsets */
131 #define KS2_CIC_CTRL 0x04
132 #define KS2_CIC_HOST_CTRL 0x0C
133 #define KS2_CIC_GLOBAL_ENABLE 0x10
134 #define KS2_CIC_SYS_ENABLE_IDX_SET 0x28
135 #define KS2_CIC_HOST_ENABLE_IDX_SET 0x34
136 #define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2))
138 #define KS2_UART0_BASE 0x02530c00
139 #define KS2_UART1_BASE 0x02531000
142 #define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
143 #define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
144 #define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
145 #define KS2_DEVCFG (KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
148 #define KS2_PSC_BASE 0x02350000
149 #define KS2_LPSC_GEM_0 15
150 #define KS2_LPSC_TETRIS 52
151 #define KS2_TETRIS_PWR_DOMAIN 31
153 /* Chip configuration unlock codes and registers */
154 #define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
155 #define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
156 #define KS2_KICK0_MAGIC 0x83e70b13
157 #define KS2_KICK1_MAGIC 0x95a4f1e0
159 /* PLL control registers */
160 #define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
161 #define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
162 #define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
163 #define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
164 #define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
165 #define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
166 #define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
167 #define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
168 #define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
169 #define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
170 #define KS2_UARTPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x390)
171 #define KS2_UARTPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x394)
173 #define KS2_PLL_CNTRL_BASE 0x02310000
174 #define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
175 #define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4)
176 #define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
177 #define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec)
178 #define KS2_RSTCTRL_KEY 0x5a69
179 #define KS2_RSTCTRL_MASK 0xffff0000
180 #define KS2_RSTCTRL_SWRST 0xfffe0000
181 #define KS2_RSTYPE_PLL_SOFT BIT(13)
184 #define KS2_SPI0_BASE 0x21000400
185 #define KS2_SPI1_BASE 0x21000600
186 #define KS2_SPI2_BASE 0x21000800
187 #define KS2_SPI_BASE KS2_SPI0_BASE
190 #define KS2_AEMIF_CNTRL_BASE 0x21000a00
191 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
193 /* Flag from ks2_debug options to check if DSPs need to stay ON */
194 #define DBG_LEAVE_DSPS_ON 0x1
197 #define KS2_MSMC_CTRL_BASE 0x0bc00000
198 #define KS2_MSMC_DATA_BASE 0x0c000000
199 #define KS2_MSMC_SEGMENT_TETRIS 8
200 #define KS2_MSMC_SEGMENT_NETCP 9
201 #define KS2_MSMC_SEGMENT_QM_PDSP 10
202 #define KS2_MSMC_SEGMENT_PCIE0 11
204 /* MSMC segment size shift bits */
205 #define KS2_MSMC_SEG_SIZE_SHIFT 12
206 #define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
207 #define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \
208 KS2_MSMC_SEG_SIZE_SHIFT)
211 #define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
212 #define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
213 #define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
216 #define KS2_QM_BASE_ADDRESS 0x23a80000
217 #define KS2_QM_CONF_BASE 0x02a02000
218 #define KS2_QM_DESC_SETUP_BASE 0x02a03000
219 #define KS2_QM_STATUS_RAM_BASE 0x02a06000
220 #define KS2_QM_INTD_CONF_BASE 0x02a0c000
221 #define KS2_QM_PDSP1_CMD_BASE 0x02a20000
222 #define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000
223 #define KS2_QM_PDSP1_IRAM_BASE 0x02a10000
224 #define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000
225 #define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
226 #define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
227 #define KS2_QM_LINK_RAM_BASE 0x00100000
228 #define KS2_QM_REGION_NUM 64
229 #define KS2_QM_QPOOL_NUM 4000
232 #define KS2_USB_SS_BASE 0x02680000
233 #define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000)
234 #define KS2_DEV_USB_PHY_BASE 0x02620738
235 #define KS2_USB_PHY_CFG_BASE 0x02630000
237 #define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
240 #define KS2_SGMII_SERDES_BASE 0x0232a000
242 /* JTAG ID register */
243 #define JTAGID_VARIANT_SHIFT 28
244 #define JTAGID_VARIANT_MASK (0xf << 28)
245 #define JTAGID_PART_NUM_SHIFT 12
246 #define JTAGID_PART_NUM_MASK (0xffff << 12)
248 /* PART NUMBER definitions */
249 #define CPU_66AK2Hx 0xb981
250 #define CPU_66AK2Ex 0xb9a6
251 #define CPU_66AK2Lx 0xb9a7
252 #define CPU_66AK2Gx 0xbb06
254 /* DEVSPEED register */
255 #define DEVSPEED_DEVSPEED_SHIFT 16
256 #define DEVSPEED_DEVSPEED_MASK (0xfff << 16)
257 #define DEVSPEED_ARMSPEED_SHIFT 0
258 #define DEVSPEED_ARMSPEED_MASK 0xfff
259 #define DEVSPEED_NUMSPDS 12
261 #ifdef CONFIG_SOC_K2HK
262 #include <asm/arch/hardware-k2hk.h>
265 #ifdef CONFIG_SOC_K2E
266 #include <asm/arch/hardware-k2e.h>
269 #ifdef CONFIG_SOC_K2L
270 #include <asm/arch/hardware-k2l.h>
273 #ifdef CONFIG_SOC_K2G
274 #include <asm/arch/hardware-k2g.h>
279 static inline u16 get_part_number(void)
281 u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
283 return (jtag_id & JTAGID_PART_NUM_MASK) >> JTAGID_PART_NUM_SHIFT;
286 static inline u8 cpu_is_k2hk(void)
288 return get_part_number() == CPU_66AK2Hx;
291 static inline u8 cpu_is_k2e(void)
293 return get_part_number() == CPU_66AK2Ex;
296 static inline u8 cpu_is_k2l(void)
298 return get_part_number() == CPU_66AK2Lx;
301 static inline u8 cpu_is_k2g(void)
303 return get_part_number() == CPU_66AK2Gx;
306 static inline u8 cpu_revision(void)
308 u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
309 u8 rev = (jtag_id & JTAGID_VARIANT_MASK) >> JTAGID_VARIANT_SHIFT;
314 int cpu_to_bus(u32 *ptr, u32 length);
315 void sdelay(unsigned long);
319 #endif /* __ASM_ARCH_HARDWARE_H */