2 * Keystone2: Architecture initialization
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/msmc.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/psc_defs.h>
18 #define MAX_PCI_PORTS 2
25 #define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
26 #define DEVCFG_MODE_SHIFT 1
28 void chip_configuration_unlock(void)
30 __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
31 __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
40 u32 base = KS2_OSR_CFG_BASE;
41 u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
43 /* Enable the OSR clock domain */
44 psc_enable_module(KS2_LPSC_OSR);
46 /* Disable OSR ECC check for all the ram banks */
47 for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
48 val = i | KS2_OSR_ECC_VEC_TRIG_RD |
49 (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
51 writel(val , base + KS2_OSR_ECC_VEC);
54 * wait till read is done.
55 * Print should be added after earlyprintk support is added.
57 for (j = 0; j < 10000; j++) {
58 val = readl(base + KS2_OSR_ECC_VEC);
59 if (val & KS2_OSR_ECC_VEC_RD_DONE)
63 ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
66 writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
67 writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
70 /* Reset OSR memory to all zeros */
71 for (i = 0; i < KS2_OSR_SIZE; i += 4)
72 writel(0, KS2_OSR_DATA_BASE + i);
74 /* Enable OSR ECC check for all the ram banks */
75 for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
77 KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
81 /* Function to set up PCIe mode */
82 static void config_pcie_mode(int pcie_port, enum pci_mode mode)
84 u32 val = __raw_readl(KS2_DEVCFG);
86 if (pcie_port >= MAX_PCI_PORTS)
90 * each pci port has two bits for mode and it starts at
91 * bit 1. So use port number to get the right bit position.
94 val &= ~(DEVCFG_MODE_MASK << pcie_port);
95 val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
96 __raw_writel(val, KS2_DEVCFG);
99 int arch_cpu_init(void)
101 chip_configuration_unlock();
104 msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
105 msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
106 msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
107 msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
109 /* Initialize the PCIe-0 to work as Root Complex */
110 config_pcie_mode(0, ROOTCOMPLEX);
111 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
112 msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
113 /* Initialize the PCIe-1 to work as Root Complex */
114 config_pcie_mode(1, ROOTCOMPLEX);
116 #ifdef CONFIG_SOC_K2L
121 * just initialise the COM2 port so that TI specific
122 * UART register PWREMU_MGMT is initialized. Linux UART
123 * driver doesn't handle this.
125 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
126 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
131 void reset_cpu(ulong addr)
133 volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
136 tmp = *rstctrl & KS2_RSTCTRL_MASK;
137 *rstctrl = tmp | KS2_RSTCTRL_KEY;
139 *rstctrl &= KS2_RSTCTRL_SWRST;
145 void enable_caches(void)
147 #ifndef CONFIG_SYS_DCACHE_OFF
148 /* Enable D-cache. I-cache is already enabled in start.S */
153 #if defined(CONFIG_DISPLAY_CPUINFO)
154 int print_cpuinfo(void)
156 u16 cpu = get_part_number();
157 u8 rev = cpu_revision();