3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Lei Wen <leiwen@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 * This file should be included in board config header file.
12 * It supports common definitions for Kirkwood platform
18 #if defined (CONFIG_KW88F6281)
19 #include <asm/arch/kw88f6281.h>
20 #elif defined (CONFIG_KW88F6192)
21 #include <asm/arch/kw88f6192.h>
23 #error "SOC Name not defined"
24 #endif /* CONFIG_KW88F6281 */
26 #include <asm/arch/soc.h>
27 #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
28 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
29 #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
32 * By default kwbimage.cfg from board specific folder is used
33 * If for some board, different configuration file need to be used,
34 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
36 #ifndef CONFIG_SYS_KWD_CONFIG
37 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
38 #endif /* CONFIG_SYS_KWD_CONFIG */
40 /* Kirkwood has 2k of Security SRAM, use it for SP */
41 #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
42 #define CONFIG_NR_DRAM_BANKS_MAX 2
44 #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
45 #define MV_UART_CONSOLE_BASE KW_UART0_BASE
46 #define MV_SATA_BASE KW_SATA_BASE
47 #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
48 #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
53 #ifdef CONFIG_CMD_NAND
54 #define CONFIG_NAND_KIRKWOOD
55 #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
56 #define NAND_ALLOW_ERASE_ALL 1
60 * SPI Flash configuration
63 #define CONFIG_HARD_SPI 1
64 #ifndef CONFIG_ENV_SPI_BUS
65 # define CONFIG_ENV_SPI_BUS 0
67 #ifndef CONFIG_ENV_SPI_CS
68 # define CONFIG_ENV_SPI_CS 0
70 #ifndef CONFIG_ENV_SPI_MAX_HZ
71 # define CONFIG_ENV_SPI_MAX_HZ 50000000
76 * Ethernet Driver configuration
79 #define CONFIG_NETCONSOLE /* include NetConsole support */
80 #define CONFIG_MII /* expose smi ove miiphy interface */
81 #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
82 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
83 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
84 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
85 #endif /* CONFIG_CMD_NET */
91 #define CONFIG_EHCI_IS_TDI
92 #endif /* CONFIG_CMD_USB */
95 * IDE Support on SATA ports
99 #define CONFIG_IDE_PREINIT
100 #define CONFIG_MVSATA_IDE_USE_PORT1
101 /* Needs byte-swapping for ATA data register */
102 #define CONFIG_IDE_SWAP_IO
103 /* Data, registers and alternate blocks are at the same offset */
104 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
105 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
106 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
107 /* Each 8-bit ATA register is aligned to a 4-bytes address */
108 #define CONFIG_SYS_ATA_STRIDE 4
109 /* Controller supports 48-bits LBA addressing */
111 /* CONFIG_IDE requires some #defines for ATA registers */
112 #define CONFIG_SYS_IDE_MAXBUS 2
113 #define CONFIG_SYS_IDE_MAXDEVICE 2
114 /* ATA registers base is at SATA controller base */
115 #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
116 #endif /* CONFIG_IDE */
121 #ifdef CONFIG_CMD_I2C
122 #ifndef CONFIG_SYS_I2C_SOFT
123 #define CONFIG_SYS_I2C
124 #define CONFIG_SYS_I2C_MVTWSI
126 #define CONFIG_SYS_I2C_SLAVE 0x0
127 #define CONFIG_SYS_I2C_SPEED 100000
130 /* Use common timer */
131 #define CONFIG_SYS_TIMER_COUNTS_DOWN
132 #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
133 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
135 #endif /* _KW_CONFIG_H */