1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
9 #include <linux/libfdt.h>
11 #include <asm/system.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
14 #include <asm/armv8/mmu.h>
17 #define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
19 #define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
20 #define MVEBU_XTAL_MODE_MASK BIT(9)
21 #define MVEBU_XTAL_MODE_OFFS 9
22 #define MVEBU_XTAL_CLOCK_25MHZ 0x0
23 #define MVEBU_XTAL_CLOCK_40MHZ 0x1
25 #define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
26 #define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
28 static struct mm_region mvebu_mem_map[] = {
34 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
38 /* SRAM, MMIO regions */
41 .size = 0x02000000UL, /* 32MiB internal registers */
42 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
49 .size = 0x02000000UL, /* 32MiB master PCI space */
50 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
59 struct mm_region *mem_map = mvebu_mem_map;
61 void reset_cpu(ulong ignored)
64 * Write magic number of 0x1d1e to North Bridge Warm Reset register
65 * to trigger warm reset
67 writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
73 * return: reference clock in MHz (25 or 40)
79 regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
82 if (regval == MVEBU_XTAL_CLOCK_25MHZ)