2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/mbus.h>
12 #include <asm/pl310.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
17 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
18 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
20 static struct mbus_win windows[] = {
22 { MBUS_SPI_BASE, MBUS_SPI_SIZE,
23 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
26 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
27 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
30 void lowlevel_init(void)
33 * Dummy implementation, we only need LOWLEVEL_INIT
34 * on Armada to configure CP15 in start.S / cpu_init_cp15()
38 void reset_cpu(unsigned long ignored)
40 struct mvebu_system_registers *reg =
41 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
43 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
44 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
49 int mvebu_soc_family(void)
51 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
53 if ((devid == SOC_MV78260_ID) || (devid == SOC_MV78460_ID))
56 if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
57 devid == SOC_88F6828_ID)
58 return MVEBU_SOC_A38X;
60 return MVEBU_SOC_UNKNOWN;
63 #if defined(CONFIG_DISPLAY_CPUINFO)
64 int print_cpuinfo(void)
66 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
67 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
92 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
101 printf("?? (%x)\n", revid);
106 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
108 case MV_88F68XX_Z1_ID:
111 case MV_88F68XX_A0_ID:
115 printf("?? (%x)\n", revid);
122 #endif /* CONFIG_DISPLAY_CPUINFO */
125 * This function initialize Controller DRAM Fastpath windows.
126 * It takes the CS size information from the 0x1500 scratch registers
127 * and sets the correct windows sizes and base addresses accordingly.
129 * These values are set in the scratch registers by the Marvell
130 * DDR3 training code, which is executed by the BootROM before the
131 * main payload (U-Boot) is executed. This training code is currently
132 * only available in the Marvell U-Boot version. It needs to be
133 * ported to mainline U-Boot SPL at some point.
135 static void update_sdram_window_sizes(void)
141 for (i = 0; i < SDRAM_MAX_CS; i++) {
142 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
144 size |= ~(SDRAM_ADDR_MASK);
146 /* Set Base Address */
147 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
148 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
151 * Check if out of max window size and resize
154 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
155 ~(SDRAM_ADDR_MASK)) | 1;
156 temp |= (size & SDRAM_ADDR_MASK);
157 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
159 base += ((u64)size + 1);
162 * Disable window if not used, otherwise this
163 * leads to overlapping enabled windows with
164 * pretty strange results
166 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
171 void mmu_disable(void)
174 "mrc p15, 0, r0, c1, c0, 0\n"
176 "mcr p15, 0, r0, c1, c0, 0\n");
179 #ifdef CONFIG_ARCH_CPU_INIT
180 static void set_cbar(u32 addr)
182 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
185 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
186 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
187 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
188 (((addr) & 0xF) << 6))
189 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
190 (((reg) & 0xF) << 2))
192 static void setup_usb_phys(void)
200 /* Setup PLL frequency */
201 /* USB REF frequency = 25 MHz */
202 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
204 /* Power up PLL and PHY channel */
205 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
207 /* Assert VCOCAL_START */
208 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
213 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
216 for (dev = 0; dev < 3; dev++) {
217 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
219 /* Assert REG_RCAL_START in channel REG 1 */
220 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
222 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
227 * This function is not called from the SPL U-Boot version
229 int arch_cpu_init(void)
231 struct pl310_regs *const pl310 =
232 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
235 * Only with disabled MMU its possible to switch the base
236 * register address on Armada 38x. Without this the SDRAM
237 * located at >= 0x4000.0000 is also not accessible, as its
238 * still locked to cache.
242 /* Linux expects the internal registers to be at 0xf1000000 */
243 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
244 set_cbar(SOC_REGS_PHY_BASE + 0xC000);
247 * From this stage on, the SoC detection is working. As we have
248 * configured the internal register base to the value used
249 * in the macros / defines in the U-Boot header (soc.h).
252 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
254 * To fully release / unlock this area from cache, we need
255 * to flush all caches and disable the L2 cache.
259 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
263 * We need to call mvebu_mbus_probe() before calling
264 * update_sdram_window_sizes() as it disables all previously
265 * configured mbus windows and then configures them as
266 * required for U-Boot. Calling update_sdram_window_sizes()
267 * without this configuration will not work, as the internal
268 * registers can't be accessed reliably because of potenial
270 * After updating the SDRAM access windows we need to call
271 * mvebu_mbus_probe() again, as this now correctly configures
272 * the SDRAM areas that are later used by the MVEBU drivers
277 * First disable all windows
279 mvebu_mbus_probe(NULL, 0);
281 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
283 * Now the SDRAM access windows can be reconfigured using
284 * the information in the SDRAM scratch pad registers
286 update_sdram_window_sizes();
290 * Finally the mbus windows can be configured with the
291 * updated SDRAM sizes
293 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
295 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
296 /* Enable GBE0, GBE1, LCD and NFC PUP */
297 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
298 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
299 NAND_PUP_EN | SPI_PUP_EN);
301 /* Configure USB PLL and PHYs on AXP */
305 /* Enable NAND and NAND arbiter */
306 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
308 /* Disable MBUS error propagation */
309 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
313 #endif /* CONFIG_ARCH_CPU_INIT */
315 u32 mvebu_get_nand_clock(void)
317 return CONFIG_SYS_MVEBU_PLL_CLOCK /
318 ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
319 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
323 * SOC specific misc init
325 #if defined(CONFIG_ARCH_MISC_INIT)
326 int arch_misc_init(void)
328 /* Nothing yet, perhaps we need something here later */
331 #endif /* CONFIG_ARCH_MISC_INIT */
333 #ifdef CONFIG_MV_SDHCI
334 int board_mmc_init(bd_t *bis)
336 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
337 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
343 #ifdef CONFIG_SCSI_AHCI_PLAT
344 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
345 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
347 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
348 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
349 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
351 static void ahci_mvebu_mbus_config(void __iomem *base)
353 const struct mbus_dram_target_info *dram;
356 dram = mvebu_mbus_dram_info();
358 for (i = 0; i < 4; i++) {
359 writel(0, base + AHCI_WINDOW_CTRL(i));
360 writel(0, base + AHCI_WINDOW_BASE(i));
361 writel(0, base + AHCI_WINDOW_SIZE(i));
364 for (i = 0; i < dram->num_cs; i++) {
365 const struct mbus_dram_window *cs = dram->cs + i;
367 writel((cs->mbus_attr << 8) |
368 (dram->mbus_dram_target_id << 4) | 1,
369 base + AHCI_WINDOW_CTRL(i));
370 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
371 writel(((cs->size - 1) & 0xffff0000),
372 base + AHCI_WINDOW_SIZE(i));
376 static void ahci_mvebu_regret_option(void __iomem *base)
379 * Enable the regret bit to allow the SATA unit to regret a
380 * request that didn't receive an acknowlegde and avoid a
383 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
384 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
389 printf("MVEBU SATA INIT\n");
390 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
391 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
392 ahci_init((void __iomem *)MVEBU_SATA0_BASE);
396 void enable_caches(void)
398 /* Avoid problem with e.g. neta ethernet driver */
399 invalidate_dcache_all();
401 /* Enable D-cache. I-cache is already enabled in start.S */
405 void v7_outer_cache_enable(void)
407 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
408 struct pl310_regs *const pl310 =
409 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
412 /* The L2 cache is already disabled at this point */
415 * For Aurora cache in no outer mode, enable via the CP15
416 * coprocessor broadcasting of cache commands to L2.
418 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
419 u |= BIT(8); /* Set the FW bit */
420 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
424 /* Enable the L2 cache */
425 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
429 void v7_outer_cache_disable(void)
431 struct pl310_regs *const pl310 =
432 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
434 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);