2 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/mbus.h>
11 #include <asm/pl310.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
16 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
17 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
19 static struct mbus_win windows[] = {
21 { MBUS_SPI_BASE, MBUS_SPI_SIZE,
22 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
25 { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
26 CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
29 void lowlevel_init(void)
32 * Dummy implementation, we only need LOWLEVEL_INIT
33 * on Armada to configure CP15 in start.S / cpu_init_cp15()
37 void reset_cpu(unsigned long ignored)
39 struct mvebu_system_registers *reg =
40 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
42 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
43 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
48 int mvebu_soc_family(void)
50 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
59 return MVEBU_SOC_A375;
64 return MVEBU_SOC_A38X;
67 return MVEBU_SOC_UNKNOWN;
70 #if defined(CONFIG_DISPLAY_CPUINFO)
72 #if defined(CONFIG_ARMADA_375)
73 /* SAR frequency values for Armada 375 */
74 static const struct sar_freq_modes sar_freq_tab[] = {
75 { 0, 0x0, 266, 133, 266 },
76 { 1, 0x0, 333, 167, 167 },
77 { 2, 0x0, 333, 167, 222 },
78 { 3, 0x0, 333, 167, 333 },
79 { 4, 0x0, 400, 200, 200 },
80 { 5, 0x0, 400, 200, 267 },
81 { 6, 0x0, 400, 200, 400 },
82 { 7, 0x0, 500, 250, 250 },
83 { 8, 0x0, 500, 250, 334 },
84 { 9, 0x0, 500, 250, 500 },
85 { 10, 0x0, 533, 267, 267 },
86 { 11, 0x0, 533, 267, 356 },
87 { 12, 0x0, 533, 267, 533 },
88 { 13, 0x0, 600, 300, 300 },
89 { 14, 0x0, 600, 300, 400 },
90 { 15, 0x0, 600, 300, 600 },
91 { 16, 0x0, 666, 333, 333 },
92 { 17, 0x0, 666, 333, 444 },
93 { 18, 0x0, 666, 333, 666 },
94 { 19, 0x0, 800, 400, 267 },
95 { 20, 0x0, 800, 400, 400 },
96 { 21, 0x0, 800, 400, 534 },
97 { 22, 0x0, 900, 450, 300 },
98 { 23, 0x0, 900, 450, 450 },
99 { 24, 0x0, 900, 450, 600 },
100 { 25, 0x0, 1000, 500, 500 },
101 { 26, 0x0, 1000, 500, 667 },
102 { 27, 0x0, 1000, 333, 500 },
103 { 28, 0x0, 400, 400, 400 },
104 { 29, 0x0, 1100, 550, 550 },
105 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
107 #elif defined(CONFIG_ARMADA_38X)
108 /* SAR frequency values for Armada 38x */
109 static const struct sar_freq_modes sar_freq_tab[] = {
110 { 0x0, 0x0, 666, 333, 333 },
111 { 0x2, 0x0, 800, 400, 400 },
112 { 0x4, 0x0, 1066, 533, 533 },
113 { 0x6, 0x0, 1200, 600, 600 },
114 { 0x8, 0x0, 1332, 666, 666 },
115 { 0xc, 0x0, 1600, 800, 800 },
116 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
119 /* SAR frequency values for Armada XP */
120 static const struct sar_freq_modes sar_freq_tab[] = {
121 { 0xa, 0x5, 800, 400, 400 },
122 { 0x1, 0x5, 1066, 533, 533 },
123 { 0x2, 0x5, 1200, 600, 600 },
124 { 0x2, 0x9, 1200, 600, 400 },
125 { 0x3, 0x5, 1333, 667, 667 },
126 { 0x4, 0x5, 1500, 750, 750 },
127 { 0x4, 0x9, 1500, 750, 500 },
128 { 0xb, 0x9, 1600, 800, 533 },
129 { 0xb, 0xa, 1600, 800, 640 },
130 { 0xb, 0x5, 1600, 800, 800 },
131 { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
135 void get_sar_freq(struct sar_freq_modes *sar_freq)
141 #if defined(CONFIG_ARMADA_375)
142 val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
144 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
146 freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
147 #if defined(SAR2_CPU_FREQ_MASK)
149 * Shift CPU0 clock frequency select bit from SAR2 register
150 * into correct position
152 freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
153 >> SAR2_CPU_FREQ_OFFS) << 3;
155 for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
156 if (sar_freq_tab[i].val == freq) {
157 #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
158 *sar_freq = sar_freq_tab[i];
164 ffc = (val & SAR_FFC_FREQ_MASK) >>
166 for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
167 if (sar_freq_tab[k].ffc == ffc) {
168 *sar_freq = sar_freq_tab[k];
177 /* SAR value not found, return 0 for frequencies */
178 *sar_freq = sar_freq_tab[i - 1];
181 int print_cpuinfo(void)
183 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
184 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
185 struct sar_freq_modes sar_freq;
216 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
225 printf("?? (%x)", revid);
230 if (mvebu_soc_family() == MVEBU_SOC_A375) {
232 case MV_88F67XX_A0_ID:
236 printf("?? (%x)", revid);
241 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
243 case MV_88F68XX_Z1_ID:
246 case MV_88F68XX_A0_ID:
250 printf("?? (%x)", revid);
255 get_sar_freq(&sar_freq);
256 printf(" at %d MHz\n", sar_freq.p_clk);
260 #endif /* CONFIG_DISPLAY_CPUINFO */
263 * This function initialize Controller DRAM Fastpath windows.
264 * It takes the CS size information from the 0x1500 scratch registers
265 * and sets the correct windows sizes and base addresses accordingly.
267 * These values are set in the scratch registers by the Marvell
268 * DDR3 training code, which is executed by the BootROM before the
269 * main payload (U-Boot) is executed. This training code is currently
270 * only available in the Marvell U-Boot version. It needs to be
271 * ported to mainline U-Boot SPL at some point.
273 static void update_sdram_window_sizes(void)
279 for (i = 0; i < SDRAM_MAX_CS; i++) {
280 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
282 size |= ~(SDRAM_ADDR_MASK);
284 /* Set Base Address */
285 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
286 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
289 * Check if out of max window size and resize
292 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
293 ~(SDRAM_ADDR_MASK)) | 1;
294 temp |= (size & SDRAM_ADDR_MASK);
295 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
297 base += ((u64)size + 1);
300 * Disable window if not used, otherwise this
301 * leads to overlapping enabled windows with
302 * pretty strange results
304 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
309 void mmu_disable(void)
312 "mrc p15, 0, r0, c1, c0, 0\n"
314 "mcr p15, 0, r0, c1, c0, 0\n");
317 #ifdef CONFIG_ARCH_CPU_INIT
318 static void set_cbar(u32 addr)
320 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
323 #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
324 #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
325 #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
326 (((addr) & 0xF) << 6))
327 #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
328 (((reg) & 0xF) << 2))
330 static void setup_usb_phys(void)
338 /* Setup PLL frequency */
339 /* USB REF frequency = 25 MHz */
340 clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
342 /* Power up PLL and PHY channel */
343 setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
345 /* Assert VCOCAL_START */
346 setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
351 * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
354 for (dev = 0; dev < 3; dev++) {
355 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
357 /* Assert REG_RCAL_START in channel REG 1 */
358 setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
360 clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
365 * This function is not called from the SPL U-Boot version
367 int arch_cpu_init(void)
369 struct pl310_regs *const pl310 =
370 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
373 * Only with disabled MMU its possible to switch the base
374 * register address on Armada 38x. Without this the SDRAM
375 * located at >= 0x4000.0000 is also not accessible, as its
376 * still locked to cache.
380 /* Linux expects the internal registers to be at 0xf1000000 */
381 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
382 set_cbar(SOC_REGS_PHY_BASE + 0xC000);
385 * From this stage on, the SoC detection is working. As we have
386 * configured the internal register base to the value used
387 * in the macros / defines in the U-Boot header (soc.h).
390 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
392 * To fully release / unlock this area from cache, we need
393 * to flush all caches and disable the L2 cache.
397 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
401 * We need to call mvebu_mbus_probe() before calling
402 * update_sdram_window_sizes() as it disables all previously
403 * configured mbus windows and then configures them as
404 * required for U-Boot. Calling update_sdram_window_sizes()
405 * without this configuration will not work, as the internal
406 * registers can't be accessed reliably because of potenial
408 * After updating the SDRAM access windows we need to call
409 * mvebu_mbus_probe() again, as this now correctly configures
410 * the SDRAM areas that are later used by the MVEBU drivers
415 * First disable all windows
417 mvebu_mbus_probe(NULL, 0);
419 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
421 * Now the SDRAM access windows can be reconfigured using
422 * the information in the SDRAM scratch pad registers
424 update_sdram_window_sizes();
428 * Finally the mbus windows can be configured with the
429 * updated SDRAM sizes
431 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
433 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
434 /* Enable GBE0, GBE1, LCD and NFC PUP */
435 clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
436 GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
437 NAND_PUP_EN | SPI_PUP_EN);
439 /* Configure USB PLL and PHYs on AXP */
443 /* Enable NAND and NAND arbiter */
444 clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
446 /* Disable MBUS error propagation */
447 clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
451 #endif /* CONFIG_ARCH_CPU_INIT */
453 u32 mvebu_get_nand_clock(void)
455 return CONFIG_SYS_MVEBU_PLL_CLOCK /
456 ((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
457 NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
461 * SOC specific misc init
463 #if defined(CONFIG_ARCH_MISC_INIT)
464 int arch_misc_init(void)
466 /* Nothing yet, perhaps we need something here later */
469 #endif /* CONFIG_ARCH_MISC_INIT */
471 #ifdef CONFIG_MV_SDHCI
472 int board_mmc_init(bd_t *bis)
474 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
475 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
481 #ifdef CONFIG_SCSI_AHCI_PLAT
482 #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
483 #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
485 #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
486 #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
487 #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
489 static void ahci_mvebu_mbus_config(void __iomem *base)
491 const struct mbus_dram_target_info *dram;
494 dram = mvebu_mbus_dram_info();
496 for (i = 0; i < 4; i++) {
497 writel(0, base + AHCI_WINDOW_CTRL(i));
498 writel(0, base + AHCI_WINDOW_BASE(i));
499 writel(0, base + AHCI_WINDOW_SIZE(i));
502 for (i = 0; i < dram->num_cs; i++) {
503 const struct mbus_dram_window *cs = dram->cs + i;
505 writel((cs->mbus_attr << 8) |
506 (dram->mbus_dram_target_id << 4) | 1,
507 base + AHCI_WINDOW_CTRL(i));
508 writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
509 writel(((cs->size - 1) & 0xffff0000),
510 base + AHCI_WINDOW_SIZE(i));
514 static void ahci_mvebu_regret_option(void __iomem *base)
517 * Enable the regret bit to allow the SATA unit to regret a
518 * request that didn't receive an acknowlegde and avoid a
521 writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
522 writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
527 printf("MVEBU SATA INIT\n");
528 ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
529 ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
530 ahci_init((void __iomem *)MVEBU_SATA0_BASE);
534 void enable_caches(void)
536 /* Avoid problem with e.g. neta ethernet driver */
537 invalidate_dcache_all();
540 * Armada 375 still has some problems with d-cache enabled in the
541 * ethernet driver (mvpp2). So lets keep the d-cache disabled
542 * until this is solved.
544 if (mvebu_soc_family() != MVEBU_SOC_A375) {
545 /* Enable D-cache. I-cache is already enabled in start.S */
550 void v7_outer_cache_enable(void)
552 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
553 struct pl310_regs *const pl310 =
554 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
557 /* The L2 cache is already disabled at this point */
560 * For Aurora cache in no outer mode, enable via the CP15
561 * coprocessor broadcasting of cache commands to L2.
563 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
564 u |= BIT(8); /* Set the FW bit */
565 asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
569 /* Enable the L2 cache */
570 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
574 void v7_outer_cache_disable(void)
576 struct pl310_regs *const pl310 =
577 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
579 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);