3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
15 #ifdef CONFIG_SYS_MVEBU_DDR_A38X
16 #include "../../../drivers/ddr/marvell/axp/xor.h"
17 #include "../../../drivers/ddr/marvell/axp/xor_regs.h"
19 #ifdef CONFIG_SYS_MVEBU_DDR_AXP
20 #include "../../../drivers/ddr/marvell/axp/xor.h"
21 #include "../../../drivers/ddr/marvell/axp/xor_regs.h"
24 DECLARE_GLOBAL_DATA_PTR;
31 struct sdram_addr_dec {
32 struct sdram_bank sdram_bank[4];
35 #define REG_CPUCS_WIN_ENABLE (1 << 0)
36 #define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
37 #define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
38 #define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
40 #define SDRAM_SIZE_MAX 0xc0000000
42 #define SCRUB_MAGIC 0xbeefdead
44 #define SCRB_XOR_UNIT 0
45 #define SCRB_XOR_CHAN 1
46 #define SCRB_XOR_WIN 0
48 #define XEBARX_BASE_OFFS 16
51 * mvebu_sdram_bar - reads SDRAM Base Address Register
53 u32 mvebu_sdram_bar(enum memory_bank bank)
55 struct sdram_addr_dec *base =
56 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
58 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
60 if ((!enable) || (bank > BANK3))
63 result = readl(&base->sdram_bank[bank].win_bar);
68 * mvebu_sdram_bs_set - writes SDRAM Bank size
70 static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
72 struct sdram_addr_dec *base =
73 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
74 /* Read current register value */
75 u32 reg = readl(&base->sdram_bank[bank].win_sz);
77 /* Clear window size */
78 reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
80 /* Set new window size */
81 reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
83 writel(reg, &base->sdram_bank[bank].win_sz);
87 * mvebu_sdram_bs - reads SDRAM Bank size
89 u32 mvebu_sdram_bs(enum memory_bank bank)
91 struct sdram_addr_dec *base =
92 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
94 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
96 if ((!enable) || (bank > BANK3))
98 result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
103 void mvebu_sdram_size_adjust(enum memory_bank bank)
107 /* probe currently equipped RAM size */
108 size = get_ram_size((void *)mvebu_sdram_bar(bank),
109 mvebu_sdram_bs(bank));
111 /* adjust SDRAM window size accordingly */
112 mvebu_sdram_bs_set(bank, size);
115 #if defined(CONFIG_SYS_MVEBU_DDR_A38X) || defined(CONFIG_SYS_MVEBU_DDR_AXP)
116 static u32 xor_ctrl_save;
117 static u32 xor_base_save;
118 static u32 xor_mask_save;
120 static void mv_xor_init2(u32 cs)
122 u32 reg, base, size, base2;
123 u32 bank_attr[4] = { 0xe00, 0xd00, 0xb00, 0x700 };
125 xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT,
127 xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT,
129 xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT,
132 /* Enable Window x for each CS */
135 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg);
138 size = mvebu_sdram_bs(cs) - 1;
140 base2 = ((base / (64 << 10)) << XEBARX_BASE_OFFS) |
142 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
146 size = (size / (64 << 10)) << 16;
147 /* Window x - size - 256 MB */
148 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size);
156 static void mv_xor_finish2(void)
158 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN),
160 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
162 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
166 static void dram_ecc_scrubbing(void)
175 * The DDR training code from the bin_hdr / SPL already
176 * scrubbed the DDR till 0x1000000. And the main U-Boot
177 * is loaded to an address < 0x1000000. So we need to
178 * skip this range to not re-scrub this area again.
180 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
181 temp |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
182 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
184 for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) {
185 size = mvebu_sdram_bs(cs) - 1;
189 total = (u64)size + 1;
190 total_mem += (u32)(total / (1 << 30));
194 /* Skip first 16 MiB */
196 start_addr = 0x1000000;
200 mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size,
201 SCRUB_MAGIC, SCRUB_MAGIC);
203 /* Wait for previous transfer completion */
204 while (mv_xor_state_get(SCRB_XOR_CHAN) != MV_IDLE)
210 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
211 temp &= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
212 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
215 static int ecc_enabled(void)
217 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
223 static void dram_ecc_scrubbing(void)
227 static int ecc_enabled(void)
238 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
240 * It is assumed that all memory banks are consecutive
242 * If the gap is found, ram_size will be reported for
243 * consecutive memory only
245 if (mvebu_sdram_bar(i) != size)
249 * Don't report more than 3GiB of SDRAM, otherwise there is no
250 * address space left for the internal registers etc.
252 size += mvebu_sdram_bs(i);
253 if (size > SDRAM_SIZE_MAX)
254 size = SDRAM_SIZE_MAX;
257 for (; i < CONFIG_NR_DRAM_BANKS; i++) {
258 /* If above loop terminated prematurely, we need to set
259 * remaining banks' start address & size as 0. Otherwise other
260 * u-boot functions and Linux kernel gets wrong values which
261 * could result in crash */
262 gd->bd->bi_dram[i].start = 0;
263 gd->bd->bi_dram[i].size = 0;
268 dram_ecc_scrubbing();
276 * If this function is not defined here,
277 * board.c alters dram bank zero configuration defined above.
279 void dram_init_banksize(void)
284 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
285 gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
286 gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
288 /* Clip the banksize to 1GiB if it exceeds the max size */
289 size += gd->bd->bi_dram[i].size;
290 if (size > SDRAM_SIZE_MAX)
291 mvebu_sdram_bs_set(i, 0x40000000);
295 #if defined(CONFIG_ARMADA_XP)
296 void board_add_ram_info(int use_default)
298 struct sar_freq_modes sar_freq;
300 get_sar_freq(&sar_freq);
301 printf(" (%d MHz, ", sar_freq.d_clk);