1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
6 #ifndef _HIGH_SPEED_ENV_SPEC_H
7 #define _HIGH_SPEED_ENV_SPEC_H
12 * For setting or clearing a certain bit (bit is a number between 0 and 31)
15 #define SET_BIT(data, bit) ((data) | (0x1 << (bit)))
16 #define CLEAR_BIT(data, bit) ((data) & (~(0x1 << (bit))))
18 #define MAX_SERDES_LANES 7 /* as in a39x */
21 /* Serdes revision 1.2 (for A38x-Z1) */
22 #define MV_SERDES_REV_1_2 0x0
23 /* Serdes revision 2.1 (for A39x-Z1, A38x-A0) */
24 #define MV_SERDES_REV_2_1 0x1
25 #define MV_SERDES_REV_NA 0xff
27 #define SERDES_REGS_LANE_BASE_OFFSET(lane) (0x800 * (lane))
29 #define PEX_X4_ENABLE_OFFS \
30 (hws_ctrl_serdes_rev_get() == MV_SERDES_REV_1_2 ? 18 : 31)
32 /* Serdes lane types */
56 /* Serdes baud rates */
58 SERDES_SPEED_1_25_GBPS,
59 SERDES_SPEED_1_5_GBPS,
60 SERDES_SPEED_2_5_GBPS,
62 SERDES_SPEED_3_125_GBPS,
65 SERDES_SPEED_6_25_GBPS,
76 SERDES_DEFAULT_MODE, /* not pex */
82 enum serdes_type serdes_type;
83 enum serdes_speed serdes_speed;
84 enum serdes_mode serdes_mode;
89 /* Serdes ref clock options */
97 /* Serdes sequences */
99 SATA_PORT_0_ONLY_POWER_UP_SEQ,
100 SATA_PORT_1_ONLY_POWER_UP_SEQ,
102 SATA_1_5_SPEED_CONFIG_SEQ,
103 SATA_3_SPEED_CONFIG_SEQ,
104 SATA_6_SPEED_CONFIG_SEQ,
105 SATA_ELECTRICAL_CONFIG_SEQ,
107 SATA_PORT_0_ONLY_TX_CONFIG_SEQ,
108 SATA_PORT_1_ONLY_TX_CONFIG_SEQ,
112 SGMII_1_25_SPEED_CONFIG_SEQ,
113 SGMII_3_125_SPEED_CONFIG_SEQ,
114 SGMII_ELECTRICAL_CONFIG_SEQ,
115 SGMII_TX_CONFIG_SEQ1,
116 SGMII_TX_CONFIG_SEQ2,
119 PEX_2_5_SPEED_CONFIG_SEQ,
120 PEX_5_SPEED_CONFIG_SEQ,
121 PEX_ELECTRICAL_CONFIG_SEQ,
126 PEX_CONFIG_REF_CLOCK_25MHZ_SEQ,
127 PEX_CONFIG_REF_CLOCK_100MHZ_SEQ,
128 PEX_CONFIG_REF_CLOCK_40MHZ_SEQ,
131 USB3_HOST_SPEED_CONFIG_SEQ,
132 USB3_DEVICE_SPEED_CONFIG_SEQ,
133 USB3_ELECTRICAL_CONFIG_SEQ,
137 USB3_DEVICE_CONFIG_SEQ,
141 SERDES_POWER_DOWN_SEQ,
144 SGMII3_1_25_SPEED_CONFIG_SEQ,
145 SGMII3_TX_CONFIG_SEQ1,
146 SGMII3_TX_CONFIG_SEQ2,
149 QSGMII_5_SPEED_CONFIG_SEQ,
150 QSGMII_ELECTRICAL_CONFIG_SEQ,
151 QSGMII_TX_CONFIG_SEQ1,
152 QSGMII_TX_CONFIG_SEQ2,
155 XAUI_3_125_SPEED_CONFIG_SEQ,
156 XAUI_ELECTRICAL_CONFIG_SEQ,
161 RXAUI_6_25_SPEED_CONFIG_SEQ,
162 RXAUI_ELECTRICAL_CONFIG_SEQ,
163 RXAUI_TX_CONFIG_SEQ1,
164 RXAUI_TX_CONFIG_SEQ2,
169 /* The different sequence types for PEX and USB3 */
173 LAST_PEX_USB_SEQ_TYPE
177 PEXSERDES_SPEED_2_5_GBPS,
178 PEXSERDES_SPEED_5_GBPS,
179 USB3SERDES_SPEED_5_GBPS_HOST,
180 USB3SERDES_SPEED_5_GBPS_DEVICE,
181 LAST_PEX_USB_SPEED_SEQ_TYPE
184 /* The different sequence types for SATA and SGMII */
189 LAST_SATA_SGMII_SEQ_TYPE
200 LAST_XAUI_RXAUI_SEQ_TYPE
204 SATASERDES_SPEED_1_5_GBPS,
205 SATASERDES_SPEED_3_GBPS,
206 SATASERDES_SPEED_6_GBPS,
207 SGMIISERDES_SPEED_1_25_GBPS,
208 SGMIISERDES_SPEED_3_125_GBPS,
209 LAST_SATA_SGMII_SPEED_SEQ_TYPE
212 extern u8 selectors_serdes_rev1_map[LAST_SERDES_TYPE][MAX_SERDES_LANES];
213 extern u8 selectors_serdes_rev2_map[LAST_SERDES_TYPE][MAX_SERDES_LANES];
215 u8 hws_ctrl_serdes_rev_get(void);
216 int mv_update_serdes_select_phy_mode_seq(void);
217 int hws_board_topology_load(struct serdes_map **serdes_map, u8 *count);
218 enum serdes_seq serdes_type_and_speed_to_speed_seq(enum serdes_type serdes_type,
219 enum serdes_speed baud_rate);
220 int hws_serdes_seq_init(void);
221 int hws_serdes_seq_db_init(void);
222 int hws_power_up_serdes_lanes(struct serdes_map *serdes_map, u8 count);
223 int hws_ctrl_high_speed_serdes_phy_config(void);
224 int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up,
225 enum serdes_type serdes_type,
226 enum serdes_speed baud_rate,
227 enum serdes_mode serdes_mode,
228 enum ref_clock ref_clock);
229 int serdes_power_up_ctrl_ext(u32 serdes_num, int serdes_power_up,
230 enum serdes_type serdes_type,
231 enum serdes_speed baud_rate,
232 enum serdes_mode serdes_mode,
233 enum ref_clock ref_clock);
234 u32 hws_serdes_silicon_ref_clock_get(void);
235 int hws_serdes_pex_ref_clock_get(enum serdes_type serdes_type,
236 enum ref_clock *ref_clock);
237 int hws_ref_clock_set(u32 serdes_num, enum serdes_type serdes_type,
238 enum ref_clock ref_clock);
239 int hws_update_serdes_phy_selectors(struct serdes_map *serdes_map, u8 count);
240 u32 hws_serdes_get_phy_selector_val(int serdes_num,
241 enum serdes_type serdes_type);
242 u32 hws_serdes_get_ref_clock_val(enum serdes_type serdes_type);
243 u32 hws_serdes_get_max_lane(void);
244 int hws_get_ext_base_addr(u32 serdes_num, u32 base_addr, u32 unit_base_offset,
245 u32 *unit_base_reg, u32 *unit_offset);
246 int hws_pex_tx_config_seq(const struct serdes_map *serdes_map, u8 count);
247 u32 hws_get_physical_serdes_num(u32 serdes_num);
248 int hws_is_serdes_active(u8 lane_num);
250 #endif /* _HIGH_SPEED_ENV_SPEC_H */