2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
4 * Based on original Kirkwood support which is
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
16 DECLARE_GLOBAL_DATA_PTR;
19 * orion5x_sdram_bar - reads SDRAM Base Address Register
21 u32 orion5x_sdram_bar(enum memory_bank bank)
23 struct orion5x_ddr_addr_decode_registers *winregs =
24 (struct orion5x_ddr_addr_decode_registers *)
28 u32 enable = 0x01 & winregs[bank].size;
30 if ((!enable) || (bank > BANK3))
33 result = winregs[bank].base;
38 /* dram_init must store complete ramsize in gd->ram_size */
39 gd->ram_size = get_ram_size(
40 (long *) orion5x_sdram_bar(0),
41 CONFIG_MAX_RAM_BANK_SIZE);
45 void dram_init_banksize (void)
49 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
50 gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
51 gd->bd->bi_dram[i].size = get_ram_size(
52 (long *) (gd->bd->bi_dram[i].start),
53 CONFIG_MAX_RAM_BANK_SIZE);