2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include "asm/arch/orion5x.h"
15 * Configuration values for SDRAM access setup
18 #define SDRAM_CONFIG 0x3148400
19 #define SDRAM_MODE 0x62
20 #define SDRAM_CONTROL 0x4041000
21 #define SDRAM_TIME_CTRL_LOW 0x11602220
22 #define SDRAM_TIME_CTRL_HI 0x40c
23 #define SDRAM_OPEN_PAGE_EN 0x0
24 /* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
25 #define SDRAM_BANK0_SIZE 0x3ff0001
26 #define SDRAM_ADDR_CTRL 0x10
28 #define SDRAM_OP_NOP 0x05
29 #define SDRAM_OP_SETMODE 0x03
31 #define SDRAM_PAD_CTRL_WR_EN 0x80000000
32 #define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
33 #define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
34 #define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
37 * For Guideline MEM-3 - Drive Strength value
40 #define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
41 #define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
44 * For Guideline MEM-4 - DQS Reference Delay Tuning
47 #define MSAR_ARMDDRCLCK_MASK 0x000000f0
48 #define MSAR_ARMDDRCLCK_H_MASK 0x00000100
50 #define MSAR_ARMDDRCLCK_333_167 0x00000000
51 #define MSAR_ARMDDRCLCK_500_167 0x00000030
52 #define MSAR_ARMDDRCLCK_667_167 0x00000060
53 #define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
54 #define MSAR_ARMDDRCLCK_400_200 0x00000010
55 #define MSAR_ARMDDRCLCK_600_200 0x00000050
56 #define MSAR_ARMDDRCLCK_800_200 0x00000070
58 #define FTDLL_DDR1_166MHZ 0x0047F001
60 #define FTDLL_DDR1_200MHZ 0x0044D001
63 * Low-level init happens right after start.S has switched to SVC32,
64 * flushed and disabled caches and disabled MMU. We're still running
65 * from the boot chip select, so the first thing SPL should do is to
66 * set up the RAM to copy U-Boot into.
73 #ifdef CONFIG_SPL_BUILD
75 /* Use 'r4 as the base for internal register accesses */
76 ldr r4, =ORION5X_REGS_PHY_BASE
78 /* move internal registers from the default 0xD0000000
79 * to their intended location, defined by SoC */
84 /* Use R3 as the base for DRAM registers */
87 /*DDR SDRAM Initialization Control */
91 /* Use R3 as the base for PCI registers */
98 /* Use R3 as the base for DRAM registers */
101 /* set all dram windows to 0 */
108 /* 1) Configure SDRAM */
109 ldr r6, =SDRAM_CONFIG
112 /* 2) Set SDRAM Control reg */
113 ldr r6, =SDRAM_CONTROL
116 /* 3) Write SDRAM address control register */
117 ldr r6, =SDRAM_ADDR_CTRL
120 /* 4) Write SDRAM bank 0 size register */
121 ldr r6, =SDRAM_BANK0_SIZE
123 /* keep other banks disabled */
125 /* 5) Write SDRAM open pages control register */
126 ldr r6, =SDRAM_OPEN_PAGE_EN
129 /* 6) Write SDRAM timing Low register */
130 ldr r6, =SDRAM_TIME_CTRL_LOW
133 /* 7) Write SDRAM timing High register */
134 ldr r6, =SDRAM_TIME_CTRL_HI
137 /* 8) Write SDRAM mode register */
138 /* The CPU must not attempt to change the SDRAM Mode register setting */
139 /* prior to DRAM controller completion of the DRAM initialization */
140 /* sequence. To guarantee this restriction, it is recommended that */
141 /* the CPU sets the SDRAM Operation register to NOP command, performs */
142 /* read polling until the register is back in Normal operation value, */
143 /* and then sets SDRAM Mode register to its new value. */
145 /* 8.1 write 'nop' to SDRAM operation */
146 ldr r6, =SDRAM_OP_NOP
149 /* 8.2 poll SDRAM operation until back in 'normal' mode. */
155 /* 8.3 Now its safe to write new value to SDRAM Mode register */
159 /* 8.4 Set new mode */
160 ldr r6, =SDRAM_OP_SETMODE
163 /* 8.5 poll SDRAM operation until back in 'normal' mode. */
169 /* DDR SDRAM Address/Control Pads Calibration */
172 /* Set Bit [31] to make the register writable */
173 orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
176 bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
177 bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
178 bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
179 bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
181 /* Get the final N locked value of driving strength [22:17] */
184 mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
185 orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
187 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
191 /* DDR SDRAM Data Pads Calibration */
194 /* Set Bit [31] to make the register writable */
195 orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
198 bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
199 bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
200 bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
201 bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
203 /* Get the final N locked value of driving strength [22:17] */
207 orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
209 /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
214 /* Implement Guideline (GL# MEM-3) Drive Strength Value */
215 /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
217 ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
219 /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
221 orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
224 /* Correct strength and disable writes again */
225 bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
226 bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
230 /* Enable writes to DDR SDRAM Data Pads Calibration register */
232 orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
235 /* Correct strength and disable writes again */
236 bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
237 bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
241 /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
242 /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
244 /* Get the "sample on reset" register for the DDR frequancy */
247 ldr r1, =MSAR_ARMDDRCLCK_MASK
250 ldr r6, =FTDLL_DDR1_166MHZ
251 cmp r1, #MSAR_ARMDDRCLCK_333_167
253 cmp r1, #MSAR_ARMDDRCLCK_500_167
255 cmp r1, #MSAR_ARMDDRCLCK_667_167
258 ldr r6, =FTDLL_DDR1_200MHZ
259 cmp r1, #MSAR_ARMDDRCLCK_400_200_1
261 cmp r1, #MSAR_ARMDDRCLCK_400_200
263 cmp r1, #MSAR_ARMDDRCLCK_600_200
265 cmp r1, #MSAR_ARMDDRCLCK_800_200
271 /* Use R3 as the base for DRAM registers */
278 /* enable for 2 GB DDR; detection should find out real amount */
284 #endif /* CONFIG_SPL_BUILD */
286 /* Return to U-Boot via saved link register */