2 * (C) Copyright 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
5 * SPDX-License-Identifier: GPL-2.0
7 * Adapted from the very similar rk3288 ddr init.
13 #include <dt-structs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/cru_rk3188.h>
21 #include <asm/arch/ddr_rk3188.h>
22 #include <asm/arch/grf_rk3188.h>
23 #include <asm/arch/pmu_rk3188.h>
24 #include <asm/arch/sdram.h>
25 #include <linux/err.h>
27 DECLARE_GLOBAL_DATA_PTR;
30 struct rk3288_ddr_pctl *pctl;
31 struct rk3288_ddr_publ *publ;
32 struct rk3188_msch *msch;
36 struct chan_info chan[1];
39 struct rk3188_cru *cru;
40 struct rk3188_grf *grf;
41 struct rk3188_sgrf *sgrf;
42 struct rk3188_pmu *pmu;
45 struct rk3188_sdram_params {
46 #if CONFIG_IS_ENABLED(OF_PLATDATA)
47 struct dtd_rockchip_rk3188_dmc of_plat;
49 struct rk3288_sdram_channel ch[2];
50 struct rk3288_sdram_pctl_timing pctl_timing;
51 struct rk3288_sdram_phy_timing phy_timing;
52 struct rk3288_base_params base;
57 const int ddrconf_table[] = {
60 * [1:0] col(9+n), assume bw=2
64 ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
65 ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
66 ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
67 ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
68 ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
69 ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
70 ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
71 ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
81 #define TEST_PATTEN 0x5aa5f00f
82 #define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
83 #define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
85 #ifdef CONFIG_SPL_BUILD
86 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
90 for (i = 0; i < n / sizeof(u32); i++) {
97 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy)
99 u32 phy_ctl_srstn_shift = 13;
100 u32 ctl_psrstn_shift = 11;
101 u32 ctl_srstn_shift = 10;
102 u32 phy_psrstn_shift = 9;
103 u32 phy_srstn_shift = 8;
105 rk_clrsetreg(&cru->cru_softrst_con[5],
106 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
107 1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
108 1 << phy_srstn_shift,
109 phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
110 ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
111 phy << phy_srstn_shift);
114 static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n)
116 u32 phy_ctl_srstn_shift = 13;
118 rk_clrsetreg(&cru->cru_softrst_con[5],
119 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
122 static void phy_pctrl_reset(struct rk3188_cru *cru,
123 struct rk3288_ddr_publ *publ,
128 ddr_reset(cru, channel, 1, 1);
130 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
131 for (i = 0; i < 4; i++)
132 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
135 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
136 for (i = 0; i < 4; i++)
137 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
140 ddr_reset(cru, channel, 1, 0);
142 ddr_reset(cru, channel, 0, 0);
146 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
151 if (freq <= 250000000) {
152 if (freq <= 150000000)
153 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
155 setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
156 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
157 for (i = 0; i < 4; i++)
158 setbits_le32(&publ->datx8[i].dxdllcr,
161 setbits_le32(&publ->pir, PIR_DLLBYP);
163 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
164 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
165 for (i = 0; i < 4; i++) {
166 clrbits_le32(&publ->datx8[i].dxdllcr,
170 clrbits_le32(&publ->pir, PIR_DLLBYP);
174 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
176 writel(DFI_INIT_START, &pctl->dfistcfg0);
177 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
179 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
180 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
183 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
184 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
185 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
186 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
187 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
188 writel(1, &pctl->dfitphyupdtype0);
190 /* cs0 and cs1 write odt enable */
191 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
193 /* odt write length */
194 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
195 /* phyupd and ctrlupd disabled */
196 writel(0, &pctl->dfiupdcfg);
199 static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable)
204 val = 1 << DDR_16BIT_EN_SHIFT;
206 rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val);
209 static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel,
214 mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT;
215 val = ddr3_mode << MSCH4_MAINDDR3_SHIFT;
216 rk_clrsetreg(&grf->soc_con2, mask, val);
219 static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable)
223 mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT;
224 val = enable << RANK_TO_ROW15_EN_SHIFT;
225 rk_clrsetreg(&grf->soc_con2, mask, val);
228 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
229 struct rk3188_sdram_params *sdram_params,
230 struct rk3188_grf *grf)
232 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
233 sizeof(sdram_params->pctl_timing));
234 switch (sdram_params->base.dramtype) {
236 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
237 writel(sdram_params->pctl_timing.tcl - 3,
238 &pctl->dfitrddataen);
240 writel(sdram_params->pctl_timing.tcl - 2,
241 &pctl->dfitrddataen);
243 writel(sdram_params->pctl_timing.tcwl - 1,
244 &pctl->dfitphywrlat);
245 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
246 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
247 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
249 ddr_set_ddr3_mode(grf, channel, true);
250 ddr_set_enable(grf, channel, true);
254 setbits_le32(&pctl->scfg, 1);
257 static void phy_cfg(const struct chan_info *chan, int channel,
258 struct rk3188_sdram_params *sdram_params)
260 struct rk3288_ddr_publ *publ = chan->publ;
261 struct rk3188_msch *msch = chan->msch;
262 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
266 dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
268 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
269 sizeof(sdram_params->phy_timing));
270 writel(sdram_params->base.noc_timing, &msch->ddrtiming);
271 writel(0x3f, &msch->readlatency);
272 writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
273 DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
274 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
275 writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
276 DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
278 writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
279 DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
282 switch (sdram_params->base.dramtype) {
284 clrbits_le32(&publ->pgcr, 0x1f);
285 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
286 DDRMD_DDR3 << DDRMD_SHIFT);
289 if (sdram_params->base.odt) {
290 /*dynamic RTT enable */
291 for (i = 0; i < 4; i++)
292 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
294 /*dynamic RTT disable */
295 for (i = 0; i < 4; i++)
296 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
300 static void phy_init(struct rk3288_ddr_publ *publ)
302 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
303 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
305 while ((readl(&publ->pgsr) &
306 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
307 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
311 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
314 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
316 while (readl(&pctl->mcmd) & START_CMD)
320 static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
321 u32 rank, u32 cmd, u32 ma, u32 op)
323 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
324 (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
327 static void memory_init(struct rk3288_ddr_publ *publ,
330 setbits_le32(&publ->pir,
331 (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
332 | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
333 | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
335 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
336 != (PGSR_IDONE | PGSR_DLDONE))
340 static void move_to_config_state(struct rk3288_ddr_publ *publ,
341 struct rk3288_ddr_pctl *pctl)
346 state = readl(&pctl->stat) & PCTL_STAT_MSK;
350 writel(WAKEUP_STATE, &pctl->sctl);
351 while ((readl(&pctl->stat) & PCTL_STAT_MSK)
355 while ((readl(&publ->pgsr) & PGSR_DLDONE)
359 * if at low power state,need wakeup first,
360 * and then enter the config, so
366 writel(CFG_STATE, &pctl->sctl);
367 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
378 static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
379 u32 n, struct rk3188_grf *grf)
381 struct rk3288_ddr_pctl *pctl = chan->pctl;
382 struct rk3288_ddr_publ *publ = chan->publ;
383 struct rk3188_msch *msch = chan->msch;
386 setbits_le32(&pctl->ppcfg, 1);
387 ddr_set_enable(grf, channel, 1);
388 setbits_le32(&msch->ddrtiming, 1 << 31);
389 /* Data Byte disable*/
390 clrbits_le32(&publ->datx8[2].dxgcr, 1);
391 clrbits_le32(&publ->datx8[3].dxgcr, 1);
393 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
394 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
396 clrbits_le32(&pctl->ppcfg, 1);
397 ddr_set_enable(grf, channel, 0);
398 clrbits_le32(&msch->ddrtiming, 1 << 31);
399 /* Data Byte enable*/
400 setbits_le32(&publ->datx8[2].dxgcr, 1);
401 setbits_le32(&publ->datx8[3].dxgcr, 1);
404 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
405 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
407 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
408 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
410 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
411 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
413 setbits_le32(&pctl->dfistcfg0, 1 << 2);
416 static int data_training(const struct chan_info *chan, int channel,
417 struct rk3188_sdram_params *sdram_params)
423 u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
424 struct rk3288_ddr_publ *publ = chan->publ;
425 struct rk3288_ddr_pctl *pctl = chan->pctl;
427 /* disable auto refresh */
428 writel(0, &pctl->trefi);
430 if (sdram_params->base.dramtype != LPDDR3)
431 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
432 rank = sdram_params->ch[channel].rank | 1;
433 for (j = 0; j < ARRAY_SIZE(step); j++) {
435 * trigger QSTRN and RVTRN
436 * clear DTDONE status
438 setbits_le32(&publ->pir, PIR_CLRSR);
441 setbits_le32(&publ->pir,
442 PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
445 /* wait echo byte DTDONE */
446 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
449 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
452 if (!(readl(&pctl->ppcfg) & 1)) {
453 while ((readl(&publ->datx8[2].dxgsr[0])
456 while ((readl(&publ->datx8[3].dxgsr[0])
460 if (readl(&publ->pgsr) &
461 (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
466 /* send some auto refresh to complement the lost while DTT */
467 for (i = 0; i < (rank > 1 ? 8 : 4); i++)
468 send_command(pctl, rank, REF_CMD, 0);
470 if (sdram_params->base.dramtype != LPDDR3)
471 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
473 /* resume auto refresh */
474 writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
479 static void move_to_access_state(const struct chan_info *chan)
481 struct rk3288_ddr_publ *publ = chan->publ;
482 struct rk3288_ddr_pctl *pctl = chan->pctl;
486 state = readl(&pctl->stat) & PCTL_STAT_MSK;
490 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
494 writel(WAKEUP_STATE, &pctl->sctl);
495 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
498 while ((readl(&publ->pgsr) & PGSR_DLDONE)
503 writel(CFG_STATE, &pctl->sctl);
504 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
508 writel(GO_STATE, &pctl->sctl);
509 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
520 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
521 struct rk3188_sdram_params *sdram_params)
523 struct rk3288_ddr_publ *publ = chan->publ;
525 if (sdram_params->ch[chnum].bk == 3)
526 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
529 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
531 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
534 static void dram_all_config(const struct dram_info *dram,
535 struct rk3188_sdram_params *sdram_params)
540 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
541 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
542 for (chan = 0; chan < sdram_params->num_channels; chan++) {
543 const struct rk3288_sdram_channel *info =
544 &sdram_params->ch[chan];
546 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
547 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
548 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
549 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
550 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
551 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
552 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
553 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
554 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
556 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
558 if (sdram_params->ch[0].rank == 2)
559 ddr_rank_2_row15en(dram->grf, 0);
561 ddr_rank_2_row15en(dram->grf, 1);
563 writel(sys_reg, &dram->pmu->sys_reg[2]);
566 static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
567 struct rk3188_sdram_params *sdram_params)
570 int need_trainig = 0;
571 const struct chan_info *chan = &dram->chan[channel];
572 struct rk3288_ddr_publ *publ = chan->publ;
574 ddr_rank_2_row15en(dram->grf, 0);
576 if (data_training(chan, channel, sdram_params) < 0) {
577 printf("first data training fail!\n");
578 reg = readl(&publ->datx8[0].dxgsr[0]);
579 /* Check the result for rank 0 */
580 if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
581 printf("data training fail!\n");
585 /* Check the result for rank 1 */
586 if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
587 sdram_params->ch[channel].rank = 1;
588 clrsetbits_le32(&publ->pgcr, 0xF << 18,
589 sdram_params->ch[channel].rank << 18);
592 reg = readl(&publ->datx8[2].dxgsr[0]);
593 if (reg & (1 << 4)) {
594 sdram_params->ch[channel].bw = 1;
595 set_bandwidth_ratio(chan, channel,
596 sdram_params->ch[channel].bw,
601 /* Assume the Die bit width are the same with the chip bit width */
602 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
605 (data_training(chan, channel, sdram_params) < 0)) {
606 if (sdram_params->base.dramtype == LPDDR3) {
607 ddr_phy_ctl_reset(dram->cru, channel, 1);
609 ddr_phy_ctl_reset(dram->cru, channel, 0);
612 printf("2nd data training failed!");
620 * Detect ram columns and rows.
621 * @dram: dram info struct
622 * @channel: channel number to handle
623 * @sdram_params: sdram parameters, function will fill in col and row values
625 * Returns 0 or negative on error.
627 static int sdram_col_row_detect(struct dram_info *dram, int channel,
628 struct rk3188_sdram_params *sdram_params)
632 const struct chan_info *chan = &dram->chan[channel];
633 struct rk3288_ddr_pctl *pctl = chan->pctl;
634 struct rk3288_ddr_publ *publ = chan->publ;
638 for (col = 11; col >= 9; col--) {
639 writel(0, CONFIG_SYS_SDRAM_BASE);
640 addr = CONFIG_SYS_SDRAM_BASE +
641 (1 << (col + sdram_params->ch[channel].bw - 1));
642 writel(TEST_PATTEN, addr);
643 if ((readl(addr) == TEST_PATTEN) &&
644 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
648 printf("Col detect error\n");
652 sdram_params->ch[channel].col = col;
655 ddr_rank_2_row15en(dram->grf, 1);
656 move_to_config_state(publ, pctl);
657 writel(1, &chan->msch->ddrconf);
658 move_to_access_state(chan);
659 /* Detect row, max 15,min13 in rk3188*/
660 for (row = 16; row >= 13; row--) {
661 writel(0, CONFIG_SYS_SDRAM_BASE);
662 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
663 writel(TEST_PATTEN, addr);
664 if ((readl(addr) == TEST_PATTEN) &&
665 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
669 printf("Row detect error\n");
672 sdram_params->ch[channel].cs1_row = row;
673 sdram_params->ch[channel].row_3_4 = 0;
674 debug("chn %d col %d, row %d\n", channel, col, row);
675 sdram_params->ch[channel].cs0_row = row;
682 static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params)
684 int i, tmp, size, ret = 0;
686 tmp = sdram_params->ch[0].col - 9;
687 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
688 tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4);
689 size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
690 for (i = 0; i < size; i++)
691 if (tmp == ddrconf_table[i])
694 printf("niu config not found\n");
697 debug("niu config %d\n", i);
698 sdram_params->base.ddrconfig = i;
704 static int sdram_init(struct dram_info *dram,
705 struct rk3188_sdram_params *sdram_params)
711 if ((sdram_params->base.dramtype == DDR3 &&
712 sdram_params->base.ddr_freq > 800000000)) {
713 printf("SDRAM frequency is too high!");
717 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
719 printf("Could not set DDR clock\n");
723 for (channel = 0; channel < 1; channel++) {
724 const struct chan_info *chan = &dram->chan[channel];
725 struct rk3288_ddr_pctl *pctl = chan->pctl;
726 struct rk3288_ddr_publ *publ = chan->publ;
728 phy_pctrl_reset(dram->cru, publ, channel);
729 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
731 dfi_cfg(pctl, sdram_params->base.dramtype);
733 pctl_cfg(channel, pctl, sdram_params, dram->grf);
735 phy_cfg(chan, channel, sdram_params);
739 writel(POWER_UP_START, &pctl->powctl);
740 while (!(readl(&pctl->powstat) & POWER_UP_DONE))
743 memory_init(publ, sdram_params->base.dramtype);
744 move_to_config_state(publ, pctl);
746 /* Using 32bit bus width for detect */
747 sdram_params->ch[channel].bw = 2;
748 set_bandwidth_ratio(chan, channel,
749 sdram_params->ch[channel].bw, dram->grf);
751 * set cs, using n=3 for detect
756 sdram_params->ch[channel].rank = 2,
757 clrsetbits_le32(&publ->pgcr, 0xF << 18,
758 (sdram_params->ch[channel].rank | 1) << 18);
760 /* DS=40ohm,ODT=155ohm */
761 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
762 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
763 0x19 << PD_OUTPUT_SHIFT;
764 writel(zqcr, &publ->zq1cr[0]);
765 writel(zqcr, &publ->zq0cr[0]);
767 /* Detect the rank and bit-width with data-training */
768 writel(1, &chan->msch->ddrconf);
769 sdram_rank_bw_detect(dram, channel, sdram_params);
771 if (sdram_params->base.dramtype == LPDDR3) {
773 writel(0, &pctl->mrrcfg0);
774 for (i = 0; i < 17; i++)
775 send_command_op(pctl, 1, MRR_CMD, i, 0);
777 writel(4, &chan->msch->ddrconf);
778 move_to_access_state(chan);
779 /* DDR3 and LPDDR3 are always 8 bank, no need detect */
780 sdram_params->ch[channel].bk = 3;
781 /* Detect Col and Row number*/
782 ret = sdram_col_row_detect(dram, channel, sdram_params);
786 /* Find NIU DDR configuration */
787 ret = sdram_get_niu_config(sdram_params);
791 dram_all_config(dram, sdram_params);
792 debug("%s done\n", __func__);
796 printf("DRAM init failed!\n");
799 #endif /* CONFIG_SPL_BUILD */
801 size_t sdram_size_mb(struct rk3188_pmu *pmu)
803 u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
804 size_t chipsize_mb = 0;
807 u32 sys_reg = readl(&pmu->sys_reg[2]);
810 chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
812 for (ch = 0; ch < chans; ch++) {
813 rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
815 col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
816 bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
817 cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
818 SYS_REG_CS0_ROW_MASK);
819 cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
820 SYS_REG_CS1_ROW_MASK);
821 bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
823 row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
824 SYS_REG_ROW_3_4_MASK;
825 chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
828 chipsize_mb += chipsize_mb >>
831 chipsize_mb = chipsize_mb * 3 / 4;
832 size_mb += chipsize_mb;
835 /* there can be no more than 2gb of memory */
836 size_mb = min(size_mb, 0x80000000 >> 20);
841 #ifdef CONFIG_SPL_BUILD
842 static int setup_sdram(struct udevice *dev)
844 struct dram_info *priv = dev_get_priv(dev);
845 struct rk3188_sdram_params *params = dev_get_platdata(dev);
847 return sdram_init(priv, params);
850 static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev)
852 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
853 struct rk3188_sdram_params *params = dev_get_platdata(dev);
854 const void *blob = gd->fdt_blob;
855 int node = dev->of_offset;
858 /* rk3188 supports only one-channel */
859 params->num_channels = 1;
860 ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
861 (u32 *)¶ms->pctl_timing,
862 sizeof(params->pctl_timing) / sizeof(u32));
864 printf("%s: Cannot read rockchip,pctl-timing\n", __func__);
867 ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
868 (u32 *)¶ms->phy_timing,
869 sizeof(params->phy_timing) / sizeof(u32));
871 printf("%s: Cannot read rockchip,phy-timing\n", __func__);
874 ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
875 (u32 *)¶ms->base,
876 sizeof(params->base) / sizeof(u32));
878 printf("%s: Cannot read rockchip,sdram-params\n", __func__);
881 ret = regmap_init_mem(dev, ¶ms->map);
888 #endif /* CONFIG_SPL_BUILD */
890 #if CONFIG_IS_ENABLED(OF_PLATDATA)
891 static int conv_of_platdata(struct udevice *dev)
893 struct rk3188_sdram_params *plat = dev_get_platdata(dev);
894 struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat;
897 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
898 sizeof(plat->pctl_timing));
899 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
900 sizeof(plat->phy_timing));
901 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
902 /* rk3188 supports dual-channel, set default channel num to 2 */
903 plat->num_channels = 1;
904 ret = regmap_init_mem_platdata(dev, of_plat->reg,
905 ARRAY_SIZE(of_plat->reg) / 2,
914 static int rk3188_dmc_probe(struct udevice *dev)
916 #ifdef CONFIG_SPL_BUILD
917 struct rk3188_sdram_params *plat = dev_get_platdata(dev);
919 struct dram_info *priv = dev_get_priv(dev);
922 struct udevice *dev_clk;
924 #if CONFIG_IS_ENABLED(OF_PLATDATA)
925 ret = conv_of_platdata(dev);
929 map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
932 priv->chan[0].msch = regmap_get_range(map, 0);
934 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
935 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
937 #ifdef CONFIG_SPL_BUILD
938 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
939 priv->chan[0].publ = regmap_get_range(plat->map, 1);
942 ret = rockchip_get_clk(&dev_clk);
945 priv->ddr_clk.id = CLK_DDR;
946 ret = clk_request(dev_clk, &priv->ddr_clk);
950 priv->cru = rockchip_get_cru();
951 if (IS_ERR(priv->cru))
952 return PTR_ERR(priv->cru);
953 #ifdef CONFIG_SPL_BUILD
954 ret = setup_sdram(dev);
958 priv->info.base = CONFIG_SYS_SDRAM_BASE;
959 priv->info.size = sdram_size_mb(priv->pmu) << 20;
964 static int rk3188_dmc_get_info(struct udevice *dev, struct ram_info *info)
966 struct dram_info *priv = dev_get_priv(dev);
973 static struct ram_ops rk3188_dmc_ops = {
974 .get_info = rk3188_dmc_get_info,
977 static const struct udevice_id rk3188_dmc_ids[] = {
978 { .compatible = "rockchip,rk3188-dmc" },
982 U_BOOT_DRIVER(dmc_rk3188) = {
983 .name = "rockchip_rk3188_dmc",
985 .of_match = rk3188_dmc_ids,
986 .ops = &rk3188_dmc_ops,
987 #ifdef CONFIG_SPL_BUILD
988 .ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata,
990 .probe = rk3188_dmc_probe,
991 .priv_auto_alloc_size = sizeof(struct dram_info),
992 #ifdef CONFIG_SPL_BUILD
993 .platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params),