git.sur5r.net Git - u-boot/blob - arch/arm/mach-rockchip/rk3188/sdram_rk3188.c

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  * Copyright 2014 Rockchip Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0
   6  *
   7  * Adapted from the very similar rk3288 ddr init.
   8  */
   9
  10 #include <common.h>
  11 #include <clk.h>
  12 #include <dm.h>
  13 #include <dt-structs.h>
  14 #include <errno.h>
  15 #include <ram.h>
  16 #include <regmap.h>
  17 #include <syscon.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/cru_rk3188.h>
  21 #include <asm/arch/ddr_rk3188.h>
  22 #include <asm/arch/grf_rk3188.h>
  23 #include <asm/arch/pmu_rk3188.h>
  24 #include <asm/arch/sdram.h>
  25 #include <linux/err.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 struct chan_info {
  30         struct rk3288_ddr_pctl *pctl;
  31         struct rk3288_ddr_publ *publ;
  32         struct rk3188_msch *msch;
  33 };
  34
  35 struct dram_info {
  36         struct chan_info chan[1];
  37         struct ram_info info;
  38         struct clk ddr_clk;
  39         struct rk3188_cru *cru;
  40         struct rk3188_grf *grf;
  41         struct rk3188_sgrf *sgrf;
  42         struct rk3188_pmu *pmu;
  43 };
  44
  45 struct rk3188_sdram_params {
  46 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  47         struct dtd_rockchip_rk3188_dmc of_plat;
  48 #endif
  49         struct rk3288_sdram_channel ch[2];
  50         struct rk3288_sdram_pctl_timing pctl_timing;
  51         struct rk3288_sdram_phy_timing phy_timing;
  52         struct rk3288_base_params base;
  53         int num_channels;
  54         struct regmap *map;
  55 };
  56
  57 const int ddrconf_table[] = {
  58         /*
  59          * [5:4] row(13+n)
  60          * [1:0] col(9+n), assume bw=2
  61          * row      col,bw
  62          */
  63         0,
  64         ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  65         ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  66         ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
  67         ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  68         ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  69         ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
  70         ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
  71         ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
  72         0,
  73         0,
  74         0,
  75         0,
  76         0,
  77         0,
  78         0,
  79 };
  80
  81 #define TEST_PATTEN     0x5aa5f00f
  82 #define DQS_GATE_TRAINING_ERROR_RANK0   (1 << 4)
  83 #define DQS_GATE_TRAINING_ERROR_RANK1   (2 << 4)
  84
  85 #ifdef CONFIG_SPL_BUILD
  86 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
  87 {
  88         int i;
  89
  90         for (i = 0; i < n / sizeof(u32); i++) {
  91                 writel(*src, dest);
  92                 src++;
  93                 dest++;
  94         }
  95 }
  96
  97 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy)
  98 {
  99         u32 phy_ctl_srstn_shift = 13;
 100         u32 ctl_psrstn_shift = 11;
 101         u32 ctl_srstn_shift = 10;
 102         u32 phy_psrstn_shift = 9;
 103         u32 phy_srstn_shift = 8;
 104
 105         rk_clrsetreg(&cru->cru_softrst_con[5],
 106                      1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
 107                      1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
 108                      1 << phy_srstn_shift,
 109                      phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
 110                      ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
 111                      phy << phy_srstn_shift);
 112 }
 113
 114 static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n)
 115 {
 116         u32 phy_ctl_srstn_shift = 13;
 117
 118         rk_clrsetreg(&cru->cru_softrst_con[5],
 119                      1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
 120 }
 121
 122 static void phy_pctrl_reset(struct rk3188_cru *cru,
 123                             struct rk3288_ddr_publ *publ,
 124                             int channel)
 125 {
 126         int i;
 127
 128         ddr_reset(cru, channel, 1, 1);
 129         udelay(1);
 130         clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
 131         for (i = 0; i < 4; i++)
 132                 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
 133
 134         udelay(10);
 135         setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
 136         for (i = 0; i < 4; i++)
 137                 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
 138
 139         udelay(10);
 140         ddr_reset(cru, channel, 1, 0);
 141         udelay(10);
 142         ddr_reset(cru, channel, 0, 0);
 143         udelay(10);
 144 }
 145
 146 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
 147         u32 freq)
 148 {
 149         int i;
 150
 151         if (freq <= 250000000) {
 152                 if (freq <= 150000000)
 153                         clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 154                 else
 155                         setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 156                 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
 157                 for (i = 0; i < 4; i++)
 158                         setbits_le32(&publ->datx8[i].dxdllcr,
 159                                      DXDLLCR_DLLDIS);
 160
 161                 setbits_le32(&publ->pir, PIR_DLLBYP);
 162         } else {
 163                 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
 164                 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
 165                 for (i = 0; i < 4; i++) {
 166                         clrbits_le32(&publ->datx8[i].dxdllcr,
 167                                      DXDLLCR_DLLDIS);
 168                 }
 169
 170                 clrbits_le32(&publ->pir, PIR_DLLBYP);
 171         }
 172 }
 173
 174 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
 175 {
 176         writel(DFI_INIT_START, &pctl->dfistcfg0);
 177         writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
 178                &pctl->dfistcfg1);
 179         writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
 180         writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
 181                &pctl->dfilpcfg0);
 182
 183         writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
 184         writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
 185         writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
 186         writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
 187         writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
 188         writel(1, &pctl->dfitphyupdtype0);
 189
 190         /* cs0 and cs1 write odt enable */
 191         writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
 192                &pctl->dfiodtcfg);
 193         /* odt write length */
 194         writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
 195         /* phyupd and ctrlupd disabled */
 196         writel(0, &pctl->dfiupdcfg);
 197 }
 198
 199 static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable)
 200 {
 201         uint val = 0;
 202
 203         if (enable)
 204                 val = 1 << DDR_16BIT_EN_SHIFT;
 205
 206         rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val);
 207 }
 208
 209 static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel,
 210                               bool ddr3_mode)
 211 {
 212         uint mask, val;
 213
 214         mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT;
 215         val = ddr3_mode << MSCH4_MAINDDR3_SHIFT;
 216         rk_clrsetreg(&grf->soc_con2, mask, val);
 217 }
 218
 219 static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable)
 220 {
 221         uint mask, val;
 222
 223         mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT;
 224         val = enable << RANK_TO_ROW15_EN_SHIFT;
 225         rk_clrsetreg(&grf->soc_con2, mask, val);
 226 }
 227
 228 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
 229                      struct rk3188_sdram_params *sdram_params,
 230                      struct rk3188_grf *grf)
 231 {
 232         copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
 233                     sizeof(sdram_params->pctl_timing));
 234         switch (sdram_params->base.dramtype) {
 235         case DDR3:
 236                 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
 237                         writel(sdram_params->pctl_timing.tcl - 3,
 238                                &pctl->dfitrddataen);
 239                 } else {
 240                         writel(sdram_params->pctl_timing.tcl - 2,
 241                                &pctl->dfitrddataen);
 242                 }
 243                 writel(sdram_params->pctl_timing.tcwl - 1,
 244                        &pctl->dfitphywrlat);
 245                 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
 246                        DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
 247                        1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
 248                        &pctl->mcfg);
 249                 ddr_set_ddr3_mode(grf, channel, true);
 250                 ddr_set_enable(grf, channel, true);
 251                 break;
 252         }
 253
 254         setbits_le32(&pctl->scfg, 1);
 255 }
 256
 257 static void phy_cfg(const struct chan_info *chan, int channel,
 258                     struct rk3188_sdram_params *sdram_params)
 259 {
 260         struct rk3288_ddr_publ *publ = chan->publ;
 261         struct rk3188_msch *msch = chan->msch;
 262         uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
 263         u32 dinit2;
 264         int i;
 265
 266         dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
 267         /* DDR PHY Timing */
 268         copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
 269                     sizeof(sdram_params->phy_timing));
 270         writel(sdram_params->base.noc_timing, &msch->ddrtiming);
 271         writel(0x3f, &msch->readlatency);
 272         writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
 273                DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
 274                8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
 275         writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
 276                DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
 277                &publ->ptr[1]);
 278         writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
 279                DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
 280                &publ->ptr[2]);
 281
 282         switch (sdram_params->base.dramtype) {
 283         case DDR3:
 284                 clrbits_le32(&publ->pgcr, 0x1f);
 285                 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
 286                                 DDRMD_DDR3 << DDRMD_SHIFT);
 287                 break;
 288         }
 289         if (sdram_params->base.odt) {
 290                 /*dynamic RTT enable */
 291                 for (i = 0; i < 4; i++)
 292                         setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
 293         } else {
 294                 /*dynamic RTT disable */
 295                 for (i = 0; i < 4; i++)
 296                         clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
 297         }
 298 }
 299
 300 static void phy_init(struct rk3288_ddr_publ *publ)
 301 {
 302         setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
 303                 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
 304         udelay(1);
 305         while ((readl(&publ->pgsr) &
 306                 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
 307                 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
 308                 ;
 309 }
 310
 311 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
 312                          u32 cmd, u32 arg)
 313 {
 314         writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
 315         udelay(1);
 316         while (readl(&pctl->mcmd) & START_CMD)
 317                 ;
 318 }
 319
 320 static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
 321                                    u32 rank, u32 cmd, u32 ma, u32 op)
 322 {
 323         send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
 324                      (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
 325 }
 326
 327 static void memory_init(struct rk3288_ddr_publ *publ,
 328                         u32 dramtype)
 329 {
 330         setbits_le32(&publ->pir,
 331                      (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
 332                       | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
 333                       | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
 334         udelay(1);
 335         while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
 336                 != (PGSR_IDONE | PGSR_DLDONE))
 337                 ;
 338 }
 339
 340 static void move_to_config_state(struct rk3288_ddr_publ *publ,
 341                                  struct rk3288_ddr_pctl *pctl)
 342 {
 343         unsigned int state;
 344
 345         while (1) {
 346                 state = readl(&pctl->stat) & PCTL_STAT_MSK;
 347
 348                 switch (state) {
 349                 case LOW_POWER:
 350                         writel(WAKEUP_STATE, &pctl->sctl);
 351                         while ((readl(&pctl->stat) & PCTL_STAT_MSK)
 352                                 != ACCESS)
 353                                 ;
 354                         /* wait DLL lock */
 355                         while ((readl(&publ->pgsr) & PGSR_DLDONE)
 356                                 != PGSR_DLDONE)
 357                                 ;
 358                         /*
 359                          * if at low power state,need wakeup first,
 360                          * and then enter the config, so
 361                          * fallthrough
 362                          */
 363                 case ACCESS:
 364                         /* fallthrough */
 365                 case INIT_MEM:
 366                         writel(CFG_STATE, &pctl->sctl);
 367                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
 368                                 ;
 369                         break;
 370                 case CONFIG:
 371                         return;
 372                 default:
 373                         break;
 374                 }
 375         }
 376 }
 377
 378 static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
 379                                 u32 n, struct rk3188_grf *grf)
 380 {
 381         struct rk3288_ddr_pctl *pctl = chan->pctl;
 382         struct rk3288_ddr_publ *publ = chan->publ;
 383         struct rk3188_msch *msch = chan->msch;
 384
 385         if (n == 1) {
 386                 setbits_le32(&pctl->ppcfg, 1);
 387                 ddr_set_enable(grf, channel, 1);
 388                 setbits_le32(&msch->ddrtiming, 1 << 31);
 389                 /* Data Byte disable*/
 390                 clrbits_le32(&publ->datx8[2].dxgcr, 1);
 391                 clrbits_le32(&publ->datx8[3].dxgcr, 1);
 392                 /* disable DLL */
 393                 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
 394                 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
 395         } else {
 396                 clrbits_le32(&pctl->ppcfg, 1);
 397                 ddr_set_enable(grf, channel, 0);
 398                 clrbits_le32(&msch->ddrtiming, 1 << 31);
 399                 /* Data Byte enable*/
 400                 setbits_le32(&publ->datx8[2].dxgcr, 1);
 401                 setbits_le32(&publ->datx8[3].dxgcr, 1);
 402
 403                 /* enable DLL */
 404                 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
 405                 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
 406                 /* reset DLL */
 407                 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
 408                 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
 409                 udelay(10);
 410                 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
 411                 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
 412         }
 413         setbits_le32(&pctl->dfistcfg0, 1 << 2);
 414 }
 415
 416 static int data_training(const struct chan_info *chan, int channel,
 417                          struct rk3188_sdram_params *sdram_params)
 418 {
 419         unsigned int j;
 420         int ret = 0;
 421         u32 rank;
 422         int i;
 423         u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
 424         struct rk3288_ddr_publ *publ = chan->publ;
 425         struct rk3288_ddr_pctl *pctl = chan->pctl;
 426
 427         /* disable auto refresh */
 428         writel(0, &pctl->trefi);
 429
 430         if (sdram_params->base.dramtype != LPDDR3)
 431                 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
 432         rank = sdram_params->ch[channel].rank | 1;
 433         for (j = 0; j < ARRAY_SIZE(step); j++) {
 434                 /*
 435                  * trigger QSTRN and RVTRN
 436                  * clear DTDONE status
 437                  */
 438                 setbits_le32(&publ->pir, PIR_CLRSR);
 439
 440                 /* trigger DTT */
 441                 setbits_le32(&publ->pir,
 442                              PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
 443                              PIR_CLRSR);
 444                 udelay(1);
 445                 /* wait echo byte DTDONE */
 446                 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
 447                         != rank)
 448                         ;
 449                 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
 450                         != rank)
 451                         ;
 452                 if (!(readl(&pctl->ppcfg) & 1)) {
 453                         while ((readl(&publ->datx8[2].dxgsr[0])
 454                                 & rank) != rank)
 455                                 ;
 456                         while ((readl(&publ->datx8[3].dxgsr[0])
 457                                 & rank) != rank)
 458                                 ;
 459                 }
 460                 if (readl(&publ->pgsr) &
 461                     (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
 462                         ret = -1;
 463                         break;
 464                 }
 465         }
 466         /* send some auto refresh to complement the lost while DTT */
 467         for (i = 0; i < (rank > 1 ? 8 : 4); i++)
 468                 send_command(pctl, rank, REF_CMD, 0);
 469
 470         if (sdram_params->base.dramtype != LPDDR3)
 471                 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
 472
 473         /* resume auto refresh */
 474         writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
 475
 476         return ret;
 477 }
 478
 479 static void move_to_access_state(const struct chan_info *chan)
 480 {
 481         struct rk3288_ddr_publ *publ = chan->publ;
 482         struct rk3288_ddr_pctl *pctl = chan->pctl;
 483         unsigned int state;
 484
 485         while (1) {
 486                 state = readl(&pctl->stat) & PCTL_STAT_MSK;
 487
 488                 switch (state) {
 489                 case LOW_POWER:
 490                         if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
 491                                         LP_TRIG_MASK) == 1)
 492                                 return;
 493
 494                         writel(WAKEUP_STATE, &pctl->sctl);
 495                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
 496                                 ;
 497                         /* wait DLL lock */
 498                         while ((readl(&publ->pgsr) & PGSR_DLDONE)
 499                                 != PGSR_DLDONE)
 500                                 ;
 501                         break;
 502                 case INIT_MEM:
 503                         writel(CFG_STATE, &pctl->sctl);
 504                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
 505                                 ;
 506                         /* fallthrough */
 507                 case CONFIG:
 508                         writel(GO_STATE, &pctl->sctl);
 509                         while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
 510                                 ;
 511                         break;
 512                 case ACCESS:
 513                         return;
 514                 default:
 515                         break;
 516                 }
 517         }
 518 }
 519
 520 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
 521                          struct rk3188_sdram_params *sdram_params)
 522 {
 523         struct rk3288_ddr_publ *publ = chan->publ;
 524
 525         if (sdram_params->ch[chnum].bk == 3)
 526                 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
 527                                 1 << PDQ_SHIFT);
 528         else
 529                 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
 530
 531         writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
 532 }
 533
 534 static void dram_all_config(const struct dram_info *dram,
 535                             struct rk3188_sdram_params *sdram_params)
 536 {
 537         unsigned int chan;
 538         u32 sys_reg = 0;
 539
 540         sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
 541         sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
 542         for (chan = 0; chan < sdram_params->num_channels; chan++) {
 543                 const struct rk3288_sdram_channel *info =
 544                         &sdram_params->ch[chan];
 545
 546                 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
 547                 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
 548                 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
 549                 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
 550                 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
 551                 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
 552                 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
 553                 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
 554                 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
 555
 556                 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
 557         }
 558         if (sdram_params->ch[0].rank == 2)
 559                 ddr_rank_2_row15en(dram->grf, 0);
 560         else
 561                 ddr_rank_2_row15en(dram->grf, 1);
 562
 563         writel(sys_reg, &dram->pmu->sys_reg[2]);
 564 }
 565
 566 static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
 567                 struct rk3188_sdram_params *sdram_params)
 568 {
 569         int reg;
 570         int need_trainig = 0;
 571         const struct chan_info *chan = &dram->chan[channel];
 572         struct rk3288_ddr_publ *publ = chan->publ;
 573
 574         ddr_rank_2_row15en(dram->grf, 0);
 575
 576         if (data_training(chan, channel, sdram_params) < 0) {
 577                 printf("first data training fail!\n");
 578                 reg = readl(&publ->datx8[0].dxgsr[0]);
 579                 /* Check the result for rank 0 */
 580                 if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
 581                         printf("data training fail!\n");
 582                         return -EIO;
 583                 }
 584
 585                 /* Check the result for rank 1 */
 586                 if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
 587                         sdram_params->ch[channel].rank = 1;
 588                         clrsetbits_le32(&publ->pgcr, 0xF << 18,
 589                                         sdram_params->ch[channel].rank << 18);
 590                         need_trainig = 1;
 591                 }
 592                 reg = readl(&publ->datx8[2].dxgsr[0]);
 593                 if (reg & (1 << 4)) {
 594                         sdram_params->ch[channel].bw = 1;
 595                         set_bandwidth_ratio(chan, channel,
 596                                             sdram_params->ch[channel].bw,
 597                                             dram->grf);
 598                         need_trainig = 1;
 599                 }
 600         }
 601         /* Assume the Die bit width are the same with the chip bit width */
 602         sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
 603
 604         if (need_trainig &&
 605             (data_training(chan, channel, sdram_params) < 0)) {
 606                 if (sdram_params->base.dramtype == LPDDR3) {
 607                         ddr_phy_ctl_reset(dram->cru, channel, 1);
 608                         udelay(10);
 609                         ddr_phy_ctl_reset(dram->cru, channel, 0);
 610                         udelay(10);
 611                 }
 612                 printf("2nd data training failed!");
 613                 return -EIO;
 614         }
 615
 616         return 0;
 617 }
 618
 619 /*
 620  * Detect ram columns and rows.
 621  * @dram: dram info struct
 622  * @channel: channel number to handle
 623  * @sdram_params: sdram parameters, function will fill in col and row values
 624  *
 625  * Returns 0 or negative on error.
 626  */
 627 static int sdram_col_row_detect(struct dram_info *dram, int channel,
 628                 struct rk3188_sdram_params *sdram_params)
 629 {
 630         int row, col;
 631         unsigned int addr;
 632         const struct chan_info *chan = &dram->chan[channel];
 633         struct rk3288_ddr_pctl *pctl = chan->pctl;
 634         struct rk3288_ddr_publ *publ = chan->publ;
 635         int ret = 0;
 636
 637         /* Detect col */
 638         for (col = 11; col >= 9; col--) {
 639                 writel(0, CONFIG_SYS_SDRAM_BASE);
 640                 addr = CONFIG_SYS_SDRAM_BASE +
 641                         (1 << (col + sdram_params->ch[channel].bw - 1));
 642                 writel(TEST_PATTEN, addr);
 643                 if ((readl(addr) == TEST_PATTEN) &&
 644                     (readl(CONFIG_SYS_SDRAM_BASE) == 0))
 645                         break;
 646         }
 647         if (col == 8) {
 648                 printf("Col detect error\n");
 649                 ret = -EINVAL;
 650                 goto out;
 651         } else {
 652                 sdram_params->ch[channel].col = col;
 653         }
 654
 655         ddr_rank_2_row15en(dram->grf, 1);
 656         move_to_config_state(publ, pctl);
 657         writel(1, &chan->msch->ddrconf);
 658         move_to_access_state(chan);
 659         /* Detect row, max 15,min13 in rk3188*/
 660         for (row = 16; row >= 13; row--) {
 661                 writel(0, CONFIG_SYS_SDRAM_BASE);
 662                 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
 663                 writel(TEST_PATTEN, addr);
 664                 if ((readl(addr) == TEST_PATTEN) &&
 665                     (readl(CONFIG_SYS_SDRAM_BASE) == 0))
 666                         break;
 667         }
 668         if (row == 12) {
 669                 printf("Row detect error\n");
 670                 ret = -EINVAL;
 671         } else {
 672                 sdram_params->ch[channel].cs1_row = row;
 673                 sdram_params->ch[channel].row_3_4 = 0;
 674                 debug("chn %d col %d, row %d\n", channel, col, row);
 675                 sdram_params->ch[channel].cs0_row = row;
 676         }
 677
 678 out:
 679         return ret;
 680 }
 681
 682 static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params)
 683 {
 684         int i, tmp, size, ret = 0;
 685
 686         tmp = sdram_params->ch[0].col - 9;
 687         tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
 688         tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4);
 689         size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
 690         for (i = 0; i < size; i++)
 691                 if (tmp == ddrconf_table[i])
 692                         break;
 693         if (i >= size) {
 694                 printf("niu config not found\n");
 695                 ret = -EINVAL;
 696         } else {
 697                 debug("niu config %d\n", i);
 698                 sdram_params->base.ddrconfig = i;
 699         }
 700
 701         return ret;
 702 }
 703
 704 static int sdram_init(struct dram_info *dram,
 705                       struct rk3188_sdram_params *sdram_params)
 706 {
 707         int channel;
 708         int zqcr;
 709         int ret;
 710
 711         if ((sdram_params->base.dramtype == DDR3 &&
 712              sdram_params->base.ddr_freq > 800000000)) {
 713                 printf("SDRAM frequency is too high!");
 714                 return -E2BIG;
 715         }
 716
 717         ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
 718         if (ret) {
 719                 printf("Could not set DDR clock\n");
 720                 return ret;
 721         }
 722
 723         for (channel = 0; channel < 1; channel++) {
 724                 const struct chan_info *chan = &dram->chan[channel];
 725                 struct rk3288_ddr_pctl *pctl = chan->pctl;
 726                 struct rk3288_ddr_publ *publ = chan->publ;
 727
 728                 phy_pctrl_reset(dram->cru, publ, channel);
 729                 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
 730
 731                 dfi_cfg(pctl, sdram_params->base.dramtype);
 732
 733                 pctl_cfg(channel, pctl, sdram_params, dram->grf);
 734
 735                 phy_cfg(chan, channel, sdram_params);
 736
 737                 phy_init(publ);
 738
 739                 writel(POWER_UP_START, &pctl->powctl);
 740                 while (!(readl(&pctl->powstat) & POWER_UP_DONE))
 741                         ;
 742
 743                 memory_init(publ, sdram_params->base.dramtype);
 744                 move_to_config_state(publ, pctl);
 745
 746                 /* Using 32bit bus width for detect */
 747                 sdram_params->ch[channel].bw = 2;
 748                 set_bandwidth_ratio(chan, channel,
 749                                     sdram_params->ch[channel].bw, dram->grf);
 750                 /*
 751                  * set cs, using n=3 for detect
 752                  * CS0, n=1
 753                  * CS1, n=2
 754                  * CS0 & CS1, n = 3
 755                  */
 756                 sdram_params->ch[channel].rank = 2,
 757                 clrsetbits_le32(&publ->pgcr, 0xF << 18,
 758                                 (sdram_params->ch[channel].rank | 1) << 18);
 759
 760                 /* DS=40ohm,ODT=155ohm */
 761                 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
 762                         2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
 763                         0x19 << PD_OUTPUT_SHIFT;
 764                 writel(zqcr, &publ->zq1cr[0]);
 765                 writel(zqcr, &publ->zq0cr[0]);
 766
 767                 /* Detect the rank and bit-width with data-training */
 768                 writel(1, &chan->msch->ddrconf);
 769                 sdram_rank_bw_detect(dram, channel, sdram_params);
 770
 771                 if (sdram_params->base.dramtype == LPDDR3) {
 772                         u32 i;
 773                         writel(0, &pctl->mrrcfg0);
 774                         for (i = 0; i < 17; i++)
 775                                 send_command_op(pctl, 1, MRR_CMD, i, 0);
 776                 }
 777                 writel(4, &chan->msch->ddrconf);
 778                 move_to_access_state(chan);
 779                 /* DDR3 and LPDDR3 are always 8 bank, no need detect */
 780                 sdram_params->ch[channel].bk = 3;
 781                 /* Detect Col and Row number*/
 782                 ret = sdram_col_row_detect(dram, channel, sdram_params);
 783                 if (ret)
 784                         goto error;
 785         }
 786         /* Find NIU DDR configuration */
 787         ret = sdram_get_niu_config(sdram_params);
 788         if (ret)
 789                 goto error;
 790
 791         dram_all_config(dram, sdram_params);
 792         debug("%s done\n", __func__);
 793
 794         return 0;
 795 error:
 796         printf("DRAM init failed!\n");
 797         hang();
 798 }
 799 #endif /* CONFIG_SPL_BUILD */
 800
 801 size_t sdram_size_mb(struct rk3188_pmu *pmu)
 802 {
 803         u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
 804         size_t chipsize_mb = 0;
 805         size_t size_mb = 0;
 806         u32 ch;
 807         u32 sys_reg = readl(&pmu->sys_reg[2]);
 808         u32 chans;
 809
 810         chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
 811
 812         for (ch = 0; ch < chans; ch++) {
 813                 rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
 814                         SYS_REG_RANK_MASK);
 815                 col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
 816                 bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
 817                 cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
 818                                 SYS_REG_CS0_ROW_MASK);
 819                 cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
 820                                 SYS_REG_CS1_ROW_MASK);
 821                 bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
 822                         SYS_REG_BW_MASK));
 823                 row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
 824                         SYS_REG_ROW_3_4_MASK;
 825                 chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
 826
 827                 if (rank > 1)
 828                         chipsize_mb += chipsize_mb >>
 829                                 (cs0_row - cs1_row);
 830                 if (row_3_4)
 831                         chipsize_mb = chipsize_mb * 3 / 4;
 832                 size_mb += chipsize_mb;
 833         }
 834
 835         /* there can be no more than 2gb of memory */
 836         size_mb = min(size_mb, 0x80000000 >> 20);
 837
 838         return size_mb;
 839 }
 840
 841 #ifdef CONFIG_SPL_BUILD
 842 static int setup_sdram(struct udevice *dev)
 843 {
 844         struct dram_info *priv = dev_get_priv(dev);
 845         struct rk3188_sdram_params *params = dev_get_platdata(dev);
 846
 847         return sdram_init(priv, params);
 848 }
 849
 850 static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev)
 851 {
 852 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 853         struct rk3188_sdram_params *params = dev_get_platdata(dev);
 854         const void *blob = gd->fdt_blob;
 855         int node = dev->of_offset;
 856         int ret;
 857
 858         /* rk3188 supports only one-channel */
 859         params->num_channels = 1;
 860         ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
 861                                    (u32 *)&params->pctl_timing,
 862                                    sizeof(params->pctl_timing) / sizeof(u32));
 863         if (ret) {
 864                 printf("%s: Cannot read rockchip,pctl-timing\n", __func__);
 865                 return -EINVAL;
 866         }
 867         ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
 868                                    (u32 *)&params->phy_timing,
 869                                    sizeof(params->phy_timing) / sizeof(u32));
 870         if (ret) {
 871                 printf("%s: Cannot read rockchip,phy-timing\n", __func__);
 872                 return -EINVAL;
 873         }
 874         ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
 875                                    (u32 *)&params->base,
 876                                    sizeof(params->base) / sizeof(u32));
 877         if (ret) {
 878                 printf("%s: Cannot read rockchip,sdram-params\n", __func__);
 879                 return -EINVAL;
 880         }
 881         ret = regmap_init_mem(dev, &params->map);
 882         if (ret)
 883                 return ret;
 884 #endif
 885
 886         return 0;
 887 }
 888 #endif /* CONFIG_SPL_BUILD */
 889
 890 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 891 static int conv_of_platdata(struct udevice *dev)
 892 {
 893         struct rk3188_sdram_params *plat = dev_get_platdata(dev);
 894         struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat;
 895         int ret;
 896
 897         memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
 898                sizeof(plat->pctl_timing));
 899         memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
 900                sizeof(plat->phy_timing));
 901         memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
 902         /* rk3188 supports dual-channel, set default channel num to 2 */
 903         plat->num_channels = 1;
 904         ret = regmap_init_mem_platdata(dev, of_plat->reg,
 905                                        ARRAY_SIZE(of_plat->reg) / 2,
 906                                        &plat->map);
 907         if (ret)
 908                 return ret;
 909
 910         return 0;
 911 }
 912 #endif
 913
 914 static int rk3188_dmc_probe(struct udevice *dev)
 915 {
 916 #ifdef CONFIG_SPL_BUILD
 917         struct rk3188_sdram_params *plat = dev_get_platdata(dev);
 918 #endif
 919         struct dram_info *priv = dev_get_priv(dev);
 920         struct regmap *map;
 921         int ret;
 922         struct udevice *dev_clk;
 923
 924 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 925         ret = conv_of_platdata(dev);
 926         if (ret)
 927                 return ret;
 928 #endif
 929         map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
 930         if (IS_ERR(map))
 931                 return PTR_ERR(map);
 932         priv->chan[0].msch = regmap_get_range(map, 0);
 933
 934         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 935         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 936
 937 #ifdef CONFIG_SPL_BUILD
 938         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
 939         priv->chan[0].publ = regmap_get_range(plat->map, 1);
 940 #endif
 941
 942         ret = rockchip_get_clk(&dev_clk);
 943         if (ret)
 944                 return ret;
 945         priv->ddr_clk.id = CLK_DDR;
 946         ret = clk_request(dev_clk, &priv->ddr_clk);
 947         if (ret)
 948                 return ret;
 949
 950         priv->cru = rockchip_get_cru();
 951         if (IS_ERR(priv->cru))
 952                 return PTR_ERR(priv->cru);
 953 #ifdef CONFIG_SPL_BUILD
 954         ret = setup_sdram(dev);
 955         if (ret)
 956                 return ret;
 957 #endif
 958         priv->info.base = CONFIG_SYS_SDRAM_BASE;
 959         priv->info.size = sdram_size_mb(priv->pmu) << 20;
 960
 961         return 0;
 962 }
 963
 964 static int rk3188_dmc_get_info(struct udevice *dev, struct ram_info *info)
 965 {
 966         struct dram_info *priv = dev_get_priv(dev);
 967
 968         *info = priv->info;
 969
 970         return 0;
 971 }
 972
 973 static struct ram_ops rk3188_dmc_ops = {
 974         .get_info = rk3188_dmc_get_info,
 975 };
 976
 977 static const struct udevice_id rk3188_dmc_ids[] = {
 978         { .compatible = "rockchip,rk3188-dmc" },
 979         { }
 980 };
 981
 982 U_BOOT_DRIVER(dmc_rk3188) = {
 983         .name = "rockchip_rk3188_dmc",
 984         .id = UCLASS_RAM,
 985         .of_match = rk3188_dmc_ids,
 986         .ops = &rk3188_dmc_ops,
 987 #ifdef CONFIG_SPL_BUILD
 988         .ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata,
 989 #endif
 990         .probe = rk3188_dmc_probe,
 991         .priv_auto_alloc_size = sizeof(struct dram_info),
 992 #ifdef CONFIG_SPL_BUILD
 993         .platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params),
 994 #endif
 995 };