git.sur5r.net Git - u-boot/blob - arch/arm/mach-rockchip/rk322x-board-spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <debug_uart.h>
   8 #include <dm.h>
   9 #include <ram.h>
  10 #include <spl.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/bootrom.h>
  13 #include <asm/arch/cru_rk322x.h>
  14 #include <asm/arch/grf_rk322x.h>
  15 #include <asm/arch/hardware.h>
  16 #include <asm/arch/timer.h>
  17 #include <asm/arch/uart.h>
  18
  19 u32 spl_boot_device(void)
  20 {
  21         return BOOT_DEVICE_MMC1;
  22 }
  23 #define GRF_BASE        0x11000000
  24 #define SGRF_BASE       0x10140000
  25
  26 #define DEBUG_UART_BASE 0x11030000
  27
  28 void board_debug_uart_init(void)
  29 {
  30         static struct rk322x_grf * const grf = (void *)GRF_BASE;
  31         enum {
  32                 GPIO1B2_SHIFT           = 4,
  33                 GPIO1B2_MASK            = 3 << GPIO1B2_SHIFT,
  34                 GPIO1B2_GPIO            = 0,
  35                 GPIO1B2_UART1_SIN,
  36                 GPIO1B2_UART21_SIN,
  37
  38                 GPIO1B1_SHIFT           = 2,
  39                 GPIO1B1_MASK            = 3 << GPIO1B1_SHIFT,
  40                 GPIO1B1_GPIO            = 0,
  41                 GPIO1B1_UART1_SOUT,
  42                 GPIO1B1_UART21_SOUT,
  43         };
  44         enum {
  45                 CON_IOMUX_UART2SEL_SHIFT= 8,
  46                 CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
  47                 CON_IOMUX_UART2SEL_2    = 0,
  48                 CON_IOMUX_UART2SEL_21,
  49         };
  50
  51         /* Enable early UART2 channel 1 on the RK322x */
  52         rk_clrsetreg(&grf->gpio1b_iomux,
  53                      GPIO1B1_MASK | GPIO1B2_MASK,
  54                      GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
  55                      GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
  56         /* Set channel C as UART2 input */
  57         rk_clrsetreg(&grf->con_iomux,
  58                      CON_IOMUX_UART2SEL_MASK,
  59                      CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
  60 }
  61
  62 #define SGRF_DDR_CON0 0x10150000
  63 void board_init_f(ulong dummy)
  64 {
  65         struct udevice *dev;
  66         int ret;
  67
  68         /*
  69          * Debug UART can be used from here if required:
  70          *
  71          * debug_uart_init();
  72          * printch('a');
  73          * printhex8(0x1234);
  74          * printascii("string");
  75          */
  76         debug_uart_init();
  77         printascii("SPL Init");
  78
  79         ret = spl_early_init();
  80         if (ret) {
  81                 debug("spl_early_init() failed: %d\n", ret);
  82                 hang();
  83         }
  84
  85         rockchip_timer_init();
  86         printf("timer init done\n");
  87         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  88         if (ret) {
  89                 printf("DRAM init failed: %d\n", ret);
  90                 return;
  91         }
  92
  93         /* Disable the ddr secure region setting to make it non-secure */
  94         rk_clrreg(SGRF_DDR_CON0, 0x4000);
  95 #if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
  96         back_to_bootrom(BROM_BOOT_NEXTSTAGE);
  97 #endif
  98 }