2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <debug_uart.h>
18 #include <asm/arch/bootrom.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/hardware.h>
21 #include <asm/arch/periph.h>
22 #include <asm/arch/sdram.h>
23 #include <asm/arch/timer.h>
24 #include <dm/pinctrl.h>
28 #include <power/regulator.h>
29 #include <power/rk8xx_pmic.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 u32 spl_boot_device(void)
35 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
36 const void *blob = gd->fdt_blob;
42 bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
43 debug("Boot device %s\n", bootdev);
47 node = fdt_path_offset(blob, bootdev);
49 debug("node=%d\n", node);
52 ret = device_get_global_by_of_offset(node, &dev);
54 debug("device at node %s/%d not found: %d\n", bootdev, node,
58 debug("Found device %s\n", dev->name);
59 switch (device_get_uclass_id(dev)) {
60 case UCLASS_SPI_FLASH:
61 return BOOT_DEVICE_SPI;
63 return BOOT_DEVICE_MMC1;
65 debug("Booting from device uclass '%s' not supported\n",
66 dev_get_uclass_name(dev));
70 #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
71 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
72 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
73 return BOOT_DEVICE_SPI;
75 return BOOT_DEVICE_MMC1;
78 u32 spl_boot_mode(const u32 boot_device)
80 return MMCSD_MODE_RAW;
83 /* read L2 control register (L2CTLR) */
84 static inline uint32_t read_l2ctlr(void)
88 asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
93 /* write L2 control register (L2CTLR) */
94 static inline void write_l2ctlr(uint32_t val)
97 * Note: L2CTLR can only be written when the L2 memory system
98 * is idle, ie before the MMU is enabled.
100 asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
104 static void configure_l2ctlr(void)
108 l2ctlr = read_l2ctlr();
109 l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
112 * Data RAM write latency: 2 cycles
113 * Data RAM read latency: 2 cycles
114 * Data RAM setup latency: 1 cycle
115 * Tag RAM write latency: 1 cycle
116 * Tag RAM read latency: 1 cycle
117 * Tag RAM setup latency: 1 cycle
119 l2ctlr |= (1 << 3 | 1 << 0);
120 write_l2ctlr(l2ctlr);
123 #ifdef CONFIG_SPL_MMC_SUPPORT
124 static int configure_emmc(struct udevice *pinctrl)
126 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
128 struct gpio_desc desc;
131 pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
134 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
135 * use the EMMC_PWREN setting.
137 ret = dm_gpio_lookup_name("D9", &desc);
139 debug("gpio ret=%d\n", ret);
142 ret = dm_gpio_request(&desc, "emmc_pwren");
144 debug("gpio_request ret=%d\n", ret);
147 ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
149 debug("gpio dir ret=%d\n", ret);
152 ret = dm_gpio_set_value(&desc, 1);
154 debug("gpio value ret=%d\n", ret);
162 #if !defined(CONFIG_SPL_OF_PLATDATA)
163 static int phycore_init(void)
165 struct udevice *pmic;
168 ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
172 #if defined(CONFIG_SPL_POWER_SUPPORT)
173 /* Increase USB input current to 2A */
174 ret = rk818_spl_configure_usb_input_current(pmic, 2000);
178 /* Close charger when USB lower then 3.26V */
179 ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
188 void board_init_f(ulong dummy)
190 struct udevice *pinctrl;
194 /* Example code showing how to enable the debug UART on RK3288 */
195 #include <asm/arch/grf_rk3288.h>
196 /* Enable early UART on the RK3288 */
197 #define GRF_BASE 0xff770000
198 struct rk3288_grf * const grf = (void *)GRF_BASE;
200 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
201 GPIO7C6_MASK << GPIO7C6_SHIFT,
202 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
203 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
205 * Debug UART can be used from here if required:
210 * printascii("string");
213 debug("\nspl:debug uart enabled in %s\n", __func__);
214 ret = spl_early_init();
216 debug("spl_early_init() failed: %d\n", ret);
220 rockchip_timer_init();
223 ret = rockchip_get_clk(&dev);
225 debug("CLK init failed: %d\n", ret);
229 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
231 debug("Pinctrl init failed: %d\n", ret);
235 #if !defined(CONFIG_SPL_OF_PLATDATA)
236 if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
237 ret = phycore_init();
239 debug("Failed to set up phycore power settings: %d\n",
246 debug("\nspl:init dram\n");
247 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
249 debug("DRAM init failed: %d\n", ret);
252 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
257 static int setup_led(void)
259 #ifdef CONFIG_SPL_LED
264 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
267 ret = led_get_by_label(led_name, &dev);
269 debug("%s: get=%d\n", __func__, ret);
272 ret = led_set_on(dev, 1);
280 void spl_board_init(void)
282 struct udevice *pinctrl;
288 debug("LED ret=%d\n", ret);
292 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
294 debug("%s: Cannot find pinctrl device\n", __func__);
298 #ifdef CONFIG_SPL_MMC_SUPPORT
299 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
301 debug("%s: Failed to set up SD card\n", __func__);
304 ret = configure_emmc(pinctrl);
306 debug("%s: Failed to set up eMMC\n", __func__);
311 /* Enable debug UART */
312 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
314 debug("%s: Failed to set up console UART\n", __func__);
318 preloader_console_init();
319 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
324 printf("spl_board_init: Error %d\n", ret);
326 /* No way to report error here */