2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <debug_uart.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/periph.h>
20 #include <asm/arch/sdram.h>
21 #include <asm/arch/timer.h>
22 #include <dm/pinctrl.h>
26 #include <power/regulator.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 u32 spl_boot_device(void)
32 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
33 const void *blob = gd->fdt_blob;
39 bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
40 debug("Boot device %s\n", bootdev);
44 node = fdt_path_offset(blob, bootdev);
46 debug("node=%d\n", node);
49 ret = device_get_global_by_of_offset(node, &dev);
51 debug("device at node %s/%d not found: %d\n", bootdev, node,
55 debug("Found device %s\n", dev->name);
56 switch (device_get_uclass_id(dev)) {
57 case UCLASS_SPI_FLASH:
58 return BOOT_DEVICE_SPI;
60 return BOOT_DEVICE_MMC1;
62 debug("Booting from device uclass '%s' not supported\n",
63 dev_get_uclass_name(dev));
67 #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
68 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
69 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
70 return BOOT_DEVICE_SPI;
72 return BOOT_DEVICE_MMC1;
75 u32 spl_boot_mode(const u32 boot_device)
77 return MMCSD_MODE_RAW;
80 /* read L2 control register (L2CTLR) */
81 static inline uint32_t read_l2ctlr(void)
85 asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
90 /* write L2 control register (L2CTLR) */
91 static inline void write_l2ctlr(uint32_t val)
94 * Note: L2CTLR can only be written when the L2 memory system
95 * is idle, ie before the MMU is enabled.
97 asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
101 static void configure_l2ctlr(void)
105 l2ctlr = read_l2ctlr();
106 l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
109 * Data RAM write latency: 2 cycles
110 * Data RAM read latency: 2 cycles
111 * Data RAM setup latency: 1 cycle
112 * Tag RAM write latency: 1 cycle
113 * Tag RAM read latency: 1 cycle
114 * Tag RAM setup latency: 1 cycle
116 l2ctlr |= (1 << 3 | 1 << 0);
117 write_l2ctlr(l2ctlr);
120 #ifdef CONFIG_SPL_MMC_SUPPORT
121 static int configure_emmc(struct udevice *pinctrl)
123 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
125 struct gpio_desc desc;
128 pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
131 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
132 * use the EMMC_PWREN setting.
134 ret = dm_gpio_lookup_name("D9", &desc);
136 debug("gpio ret=%d\n", ret);
139 ret = dm_gpio_request(&desc, "emmc_pwren");
141 debug("gpio_request ret=%d\n", ret);
144 ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
146 debug("gpio dir ret=%d\n", ret);
149 ret = dm_gpio_set_value(&desc, 1);
151 debug("gpio value ret=%d\n", ret);
158 extern void back_to_bootrom(void);
159 void board_init_f(ulong dummy)
161 struct udevice *pinctrl;
165 /* Example code showing how to enable the debug UART on RK3288 */
167 #include <asm/arch/grf_rk3288.h>
168 /* Enable early UART on the RK3288 */
169 #define GRF_BASE 0xff770000
170 struct rk3288_grf * const grf = (void *)GRF_BASE;
172 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
173 GPIO7C6_MASK << GPIO7C6_SHIFT,
174 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
175 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
177 * Debug UART can be used from here if required:
182 * printascii("string");
189 debug("spl_init() failed: %d\n", ret);
193 rockchip_timer_init();
196 ret = rockchip_get_clk(&dev);
198 debug("CLK init failed: %d\n", ret);
202 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
204 debug("Pinctrl init failed: %d\n", ret);
208 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
210 debug("DRAM init failed: %d\n", ret);
213 #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
218 static int setup_led(void)
220 #ifdef CONFIG_SPL_LED
225 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
228 ret = led_get_by_label(led_name, &dev);
230 debug("%s: get=%d\n", __func__, ret);
233 ret = led_set_on(dev, 1);
241 void spl_board_init(void)
243 struct udevice *pinctrl;
249 debug("LED ret=%d\n", ret);
253 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
255 debug("%s: Cannot find pinctrl device\n", __func__);
259 #ifdef CONFIG_SPL_MMC_SUPPORT
260 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
262 debug("%s: Failed to set up SD card\n", __func__);
265 ret = configure_emmc(pinctrl);
267 debug("%s: Failed to set up eMMC\n", __func__);
272 /* Enable debug UART */
273 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
275 debug("%s: Failed to set up console UART\n", __func__);
279 preloader_console_init();
280 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
285 printf("spl_board_init: Error %d\n", ret);
287 /* No way to report error here */