2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <debug_uart.h>
17 #include <asm/arch/bootrom.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/periph.h>
21 #include <asm/arch/sdram.h>
22 #include <asm/arch/timer.h>
23 #include <dm/pinctrl.h>
27 #include <power/regulator.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 u32 spl_boot_device(void)
33 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
34 const void *blob = gd->fdt_blob;
40 bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
41 debug("Boot device %s\n", bootdev);
45 node = fdt_path_offset(blob, bootdev);
47 debug("node=%d\n", node);
50 ret = device_get_global_by_of_offset(node, &dev);
52 debug("device at node %s/%d not found: %d\n", bootdev, node,
56 debug("Found device %s\n", dev->name);
57 switch (device_get_uclass_id(dev)) {
58 case UCLASS_SPI_FLASH:
59 return BOOT_DEVICE_SPI;
61 return BOOT_DEVICE_MMC1;
63 debug("Booting from device uclass '%s' not supported\n",
64 dev_get_uclass_name(dev));
68 #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
69 defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
70 defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
71 return BOOT_DEVICE_SPI;
73 return BOOT_DEVICE_MMC1;
76 u32 spl_boot_mode(const u32 boot_device)
78 return MMCSD_MODE_RAW;
81 /* read L2 control register (L2CTLR) */
82 static inline uint32_t read_l2ctlr(void)
86 asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
91 /* write L2 control register (L2CTLR) */
92 static inline void write_l2ctlr(uint32_t val)
95 * Note: L2CTLR can only be written when the L2 memory system
96 * is idle, ie before the MMU is enabled.
98 asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
102 static void configure_l2ctlr(void)
106 l2ctlr = read_l2ctlr();
107 l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
110 * Data RAM write latency: 2 cycles
111 * Data RAM read latency: 2 cycles
112 * Data RAM setup latency: 1 cycle
113 * Tag RAM write latency: 1 cycle
114 * Tag RAM read latency: 1 cycle
115 * Tag RAM setup latency: 1 cycle
117 l2ctlr |= (1 << 3 | 1 << 0);
118 write_l2ctlr(l2ctlr);
121 #ifdef CONFIG_SPL_MMC_SUPPORT
122 static int configure_emmc(struct udevice *pinctrl)
124 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
126 struct gpio_desc desc;
129 pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
132 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
133 * use the EMMC_PWREN setting.
135 ret = dm_gpio_lookup_name("D9", &desc);
137 debug("gpio ret=%d\n", ret);
140 ret = dm_gpio_request(&desc, "emmc_pwren");
142 debug("gpio_request ret=%d\n", ret);
145 ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
147 debug("gpio dir ret=%d\n", ret);
150 ret = dm_gpio_set_value(&desc, 1);
152 debug("gpio value ret=%d\n", ret);
160 void board_init_f(ulong dummy)
162 struct udevice *pinctrl;
166 /* Example code showing how to enable the debug UART on RK3288 */
168 #include <asm/arch/grf_rk3288.h>
169 /* Enable early UART on the RK3288 */
170 #define GRF_BASE 0xff770000
171 struct rk3288_grf * const grf = (void *)GRF_BASE;
173 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
174 GPIO7C6_MASK << GPIO7C6_SHIFT,
175 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
176 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
178 * Debug UART can be used from here if required:
183 * printascii("string");
188 ret = spl_early_init();
190 debug("spl_early_init() failed: %d\n", ret);
194 rockchip_timer_init();
197 ret = rockchip_get_clk(&dev);
199 debug("CLK init failed: %d\n", ret);
203 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
205 debug("Pinctrl init failed: %d\n", ret);
209 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
211 debug("DRAM init failed: %d\n", ret);
214 #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
219 static int setup_led(void)
221 #ifdef CONFIG_SPL_LED
226 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
229 ret = led_get_by_label(led_name, &dev);
231 debug("%s: get=%d\n", __func__, ret);
234 ret = led_set_on(dev, 1);
242 void spl_board_init(void)
244 struct udevice *pinctrl;
250 debug("LED ret=%d\n", ret);
254 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
256 debug("%s: Cannot find pinctrl device\n", __func__);
260 #ifdef CONFIG_SPL_MMC_SUPPORT
261 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
263 debug("%s: Failed to set up SD card\n", __func__);
266 ret = configure_emmc(pinctrl);
268 debug("%s: Failed to set up eMMC\n", __func__);
273 /* Enable debug UART */
274 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
276 debug("%s: Failed to set up console UART\n", __func__);
280 preloader_console_init();
281 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
286 printf("spl_board_init: Error %d\n", ret);
288 /* No way to report error here */