2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/periph.h>
15 #include <asm/arch/pmu_rk3288.h>
16 #include <asm/arch/qos_rk3288.h>
17 #include <asm/arch/boot_mode.h>
19 #include <dm/pinctrl.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <power/regulator.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define PMU_BASE 0xff730000
27 static void setup_boot_mode(void)
29 struct rk3288_pmu *const pmu = (void *)PMU_BASE;
30 int boot_mode = readl(&pmu->sys_reg[0]);
32 debug("boot mode %x.\n", boot_mode);
35 writel(BOOT_NORMAL, &pmu->sys_reg[0]);
39 printf("enter fastboot!\n");
40 env_set("preboot", "setenv preboot; fastboot usb0");
43 printf("enter UMS!\n");
44 env_set("preboot", "setenv preboot; if mmc dev 0;"
45 "then ums mmc 0; else ums mmc 1;fi");
50 __weak int rk_board_late_init(void)
55 int rk3288_qos_init(void)
57 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
58 /* set vop qos to higher priority */
59 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
60 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
62 if (!fdt_node_check_compatible(gd->fdt_blob, 0,
63 "rockchip,rk3288-tinker"))
65 /* set isp qos to higher priority */
66 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
67 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
68 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
73 int board_late_init(void)
78 return rk_board_late_init();
81 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
82 static int veyron_init(void)
88 ret = regulator_get_by_platname("vdd_arm", &dev);
90 debug("Cannot set regulator name\n");
94 /* Slowly raise to max CPU voltage to prevent overshoot */
95 ret = regulator_set_value(dev, 1200000);
98 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
99 ret = regulator_set_value(dev, 1400000);
102 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
104 ret = rockchip_get_clk(&clk.dev);
108 ret = clk_set_rate(&clk, 1800000000);
109 if (IS_ERR_VALUE(ret))
118 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
119 struct udevice *pinctrl;
123 * We need to implement sdcard iomux here for the further
124 * initlization, otherwise, it'll hit sdcard command sending
127 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
129 debug("%s: Cannot find pinctrl device\n", __func__);
132 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
134 debug("%s: Failed to set up SD card\n", __func__);
140 printf("board_init: Error %d\n", ret);
142 /* No way to report error here */
149 /* We do some SoC one time setting here */
150 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
160 #ifndef CONFIG_SYS_DCACHE_OFF
161 void enable_caches(void)
163 /* Enable D-cache. I-cache is already enabled in start.S */
168 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
170 #include <usb/dwc2_udc.h>
172 static struct dwc2_plat_otg_data rk3288_otg_data = {
178 int board_usb_init(int index, enum usb_init_type init)
182 bool matched = false;
183 const void *blob = gd->fdt_blob;
186 /* find the usb_otg node */
187 node = fdt_node_offset_by_compatible(blob, -1,
188 "rockchip,rk3288-usb");
191 mode = fdt_getprop(blob, node, "dr_mode", NULL);
192 if (mode && strcmp(mode, "otg") == 0) {
197 node = fdt_node_offset_by_compatible(blob, node,
198 "rockchip,rk3288-usb");
201 debug("Not found usb_otg device\n");
204 rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
206 node = fdtdec_lookup_phandle(blob, node, "phys");
208 debug("Not found usb phy device\n");
212 phy_node = fdt_parent_offset(blob, node);
214 debug("Not found usb phy device\n");
218 rk3288_otg_data.phy_of_node = phy_node;
219 grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
221 /* find the grf node */
222 node = fdt_node_offset_by_compatible(blob, -1,
223 "rockchip,rk3288-grf");
225 debug("Not found grf device\n");
228 rk3288_otg_data.regs_phy = grf_phy_offset +
229 fdtdec_get_addr(blob, node, "reg");
231 return dwc2_udc_probe(&rk3288_otg_data);
234 int board_usb_cleanup(int index, enum usb_init_type init)
240 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
243 static const struct {
250 { "cpll", CLK_CODEC },
251 { "gpll", CLK_GENERAL },
252 #ifdef CONFIG_ROCKCHIP_RK3036
261 ret = rockchip_get_clk(&dev);
263 printf("clk-uclass not found\n");
267 for (i = 0; i < ARRAY_SIZE(clks); i++) {
272 ret = clk_request(dev, &clk);
276 rate = clk_get_rate(&clk);
277 printf("%s: %lu\n", clks[i].name, rate);
286 clock, 2, 1, do_clock,
287 "display information about clocks",
291 #define GRF_SOC_CON2 0xff77024c
293 int board_early_init_f(void)
295 struct udevice *pinctrl;
300 * This init is done in SPL, but when chain-loading U-Boot SPL will
301 * have been skipped. Allow the clock driver to check if it needs
304 ret = rockchip_get_clk(&dev);
306 debug("CLK init failed: %d\n", ret);
309 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
311 debug("%s: Cannot find pinctrl device\n", __func__);
315 /* Enable debug UART */
316 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
318 debug("%s: Failed to set up console UART\n", __func__);
321 rk_setreg(GRF_SOC_CON2, 1 << 0);