2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cru_rk3288.h>
15 #include <asm/arch/periph.h>
16 #include <asm/arch/pmu_rk3288.h>
17 #include <asm/arch/qos_rk3288.h>
18 #include <asm/arch/boot_mode.h>
20 #include <dm/pinctrl.h>
21 #include <dt-bindings/clock/rk3288-cru.h>
22 #include <power/regulator.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define PMU_BASE 0xff730000
28 static void setup_boot_mode(void)
30 struct rk3288_pmu *const pmu = (void *)PMU_BASE;
31 int boot_mode = readl(&pmu->sys_reg[0]);
33 debug("boot mode %x.\n", boot_mode);
36 writel(BOOT_NORMAL, &pmu->sys_reg[0]);
40 printf("enter fastboot!\n");
41 env_set("preboot", "setenv preboot; fastboot usb0");
44 printf("enter UMS!\n");
45 env_set("preboot", "setenv preboot; if mmc dev 0;"
46 "then ums mmc 0; else ums mmc 1;fi");
51 __weak int rk_board_late_init(void)
56 int rk3288_qos_init(void)
58 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
59 /* set vop qos to higher priority */
60 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
61 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
63 if (!fdt_node_check_compatible(gd->fdt_blob, 0,
64 "rockchip,rk3288-tinker"))
66 /* set isp qos to higher priority */
67 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
68 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
69 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
74 static void rk3288_detect_reset_reason(void)
76 struct rk3288_cru *cru = rockchip_get_cru();
82 switch (cru->cru_glb_rst_st) {
90 case FST_GLB_TSADC_RST_ST:
91 case SND_GLB_TSADC_RST_ST:
94 case FST_GLB_WDT_RST_ST:
95 case SND_GLB_WDT_RST_ST:
99 reason = "unknown reset";
102 env_set("reset_reason", reason);
105 * Clear cru_glb_rst_st, so we can determine the last reset cause
106 * for following resets.
108 rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
111 int board_late_init(void)
115 rk3288_detect_reset_reason();
117 return rk_board_late_init();
120 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
121 static int veyron_init(void)
127 ret = regulator_get_by_platname("vdd_arm", &dev);
129 debug("Cannot set regulator name\n");
133 /* Slowly raise to max CPU voltage to prevent overshoot */
134 ret = regulator_set_value(dev, 1200000);
137 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
138 ret = regulator_set_value(dev, 1400000);
141 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
143 ret = rockchip_get_clk(&clk.dev);
147 ret = clk_set_rate(&clk, 1800000000);
148 if (IS_ERR_VALUE(ret))
157 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
158 struct udevice *pinctrl;
162 * We need to implement sdcard iomux here for the further
163 * initlization, otherwise, it'll hit sdcard command sending
166 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
168 debug("%s: Cannot find pinctrl device\n", __func__);
171 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
173 debug("%s: Failed to set up SD card\n", __func__);
179 printf("board_init: Error %d\n", ret);
181 /* No way to report error here */
188 /* We do some SoC one time setting here */
189 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
199 #ifndef CONFIG_SYS_DCACHE_OFF
200 void enable_caches(void)
202 /* Enable D-cache. I-cache is already enabled in start.S */
207 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
209 #include <usb/dwc2_udc.h>
211 static struct dwc2_plat_otg_data rk3288_otg_data = {
217 int board_usb_init(int index, enum usb_init_type init)
221 bool matched = false;
222 const void *blob = gd->fdt_blob;
225 /* find the usb_otg node */
226 node = fdt_node_offset_by_compatible(blob, -1,
227 "rockchip,rk3288-usb");
230 mode = fdt_getprop(blob, node, "dr_mode", NULL);
231 if (mode && strcmp(mode, "otg") == 0) {
236 node = fdt_node_offset_by_compatible(blob, node,
237 "rockchip,rk3288-usb");
240 debug("Not found usb_otg device\n");
243 rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
245 node = fdtdec_lookup_phandle(blob, node, "phys");
247 debug("Not found usb phy device\n");
251 phy_node = fdt_parent_offset(blob, node);
253 debug("Not found usb phy device\n");
257 rk3288_otg_data.phy_of_node = phy_node;
258 grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
260 /* find the grf node */
261 node = fdt_node_offset_by_compatible(blob, -1,
262 "rockchip,rk3288-grf");
264 debug("Not found grf device\n");
267 rk3288_otg_data.regs_phy = grf_phy_offset +
268 fdtdec_get_addr(blob, node, "reg");
270 return dwc2_udc_probe(&rk3288_otg_data);
273 int board_usb_cleanup(int index, enum usb_init_type init)
279 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
282 static const struct {
289 { "cpll", CLK_CODEC },
290 { "gpll", CLK_GENERAL },
291 #ifdef CONFIG_ROCKCHIP_RK3036
300 ret = rockchip_get_clk(&dev);
302 printf("clk-uclass not found\n");
306 for (i = 0; i < ARRAY_SIZE(clks); i++) {
311 ret = clk_request(dev, &clk);
315 rate = clk_get_rate(&clk);
316 printf("%s: %lu\n", clks[i].name, rate);
325 clock, 2, 1, do_clock,
326 "display information about clocks",
330 #define GRF_SOC_CON2 0xff77024c
332 int board_early_init_f(void)
334 struct udevice *pinctrl;
339 * This init is done in SPL, but when chain-loading U-Boot SPL will
340 * have been skipped. Allow the clock driver to check if it needs
343 ret = rockchip_get_clk(&dev);
345 debug("CLK init failed: %d\n", ret);
348 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
350 debug("%s: Cannot find pinctrl device\n", __func__);
354 /* Enable debug UART */
355 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
357 debug("%s: Failed to set up console UART\n", __func__);
360 rk_setreg(GRF_SOC_CON2, 1 << 0);