1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2015 Google, Inc
12 #include <asm/arch/clock.h>
13 #include <asm/arch/cru_rk3288.h>
14 #include <asm/arch/periph.h>
15 #include <asm/arch/pmu_rk3288.h>
16 #include <asm/arch/qos_rk3288.h>
17 #include <asm/arch/boot_mode.h>
19 #include <dm/pinctrl.h>
20 #include <dt-bindings/clock/rk3288-cru.h>
21 #include <power/regulator.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 __weak int rk_board_late_init(void)
30 int rk3288_qos_init(void)
32 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
33 /* set vop qos to higher priority */
34 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
35 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
37 if (!fdt_node_check_compatible(gd->fdt_blob, 0,
38 "rockchip,rk3288-tinker"))
40 /* set isp qos to higher priority */
41 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
42 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
43 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
48 static void rk3288_detect_reset_reason(void)
50 struct rk3288_cru *cru = rockchip_get_cru();
56 switch (cru->cru_glb_rst_st) {
64 case FST_GLB_TSADC_RST_ST:
65 case SND_GLB_TSADC_RST_ST:
68 case FST_GLB_WDT_RST_ST:
69 case SND_GLB_WDT_RST_ST:
73 reason = "unknown reset";
76 env_set("reset_reason", reason);
79 * Clear cru_glb_rst_st, so we can determine the last reset cause
80 * for following resets.
82 rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
85 int board_late_init(void)
89 rk3288_detect_reset_reason();
91 return rk_board_late_init();
94 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
95 static int veyron_init(void)
101 ret = regulator_get_by_platname("vdd_arm", &dev);
103 debug("Cannot set regulator name\n");
107 /* Slowly raise to max CPU voltage to prevent overshoot */
108 ret = regulator_set_value(dev, 1200000);
111 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
112 ret = regulator_set_value(dev, 1400000);
115 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
117 ret = rockchip_get_clk(&clk.dev);
121 ret = clk_set_rate(&clk, 1800000000);
122 if (IS_ERR_VALUE(ret))
131 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
132 struct udevice *pinctrl;
136 * We need to implement sdcard iomux here for the further
137 * initlization, otherwise, it'll hit sdcard command sending
140 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
142 debug("%s: Cannot find pinctrl device\n", __func__);
145 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
147 debug("%s: Failed to set up SD card\n", __func__);
153 printf("board_init: Error %d\n", ret);
155 /* No way to report error here */
162 /* We do some SoC one time setting here */
163 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
173 #ifndef CONFIG_SYS_DCACHE_OFF
174 void enable_caches(void)
176 /* Enable D-cache. I-cache is already enabled in start.S */
181 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
183 #include <usb/dwc2_udc.h>
185 static struct dwc2_plat_otg_data rk3288_otg_data = {
191 int board_usb_init(int index, enum usb_init_type init)
195 bool matched = false;
196 const void *blob = gd->fdt_blob;
199 /* find the usb_otg node */
200 node = fdt_node_offset_by_compatible(blob, -1,
201 "rockchip,rk3288-usb");
204 mode = fdt_getprop(blob, node, "dr_mode", NULL);
205 if (mode && strcmp(mode, "otg") == 0) {
210 node = fdt_node_offset_by_compatible(blob, node,
211 "rockchip,rk3288-usb");
214 debug("Not found usb_otg device\n");
217 rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
219 node = fdtdec_lookup_phandle(blob, node, "phys");
221 debug("Not found usb phy device\n");
225 phy_node = fdt_parent_offset(blob, node);
227 debug("Not found usb phy device\n");
231 rk3288_otg_data.phy_of_node = phy_node;
232 grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
234 /* find the grf node */
235 node = fdt_node_offset_by_compatible(blob, -1,
236 "rockchip,rk3288-grf");
238 debug("Not found grf device\n");
241 rk3288_otg_data.regs_phy = grf_phy_offset +
242 fdtdec_get_addr(blob, node, "reg");
244 return dwc2_udc_probe(&rk3288_otg_data);
247 int board_usb_cleanup(int index, enum usb_init_type init)
253 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
256 static const struct {
263 { "cpll", CLK_CODEC },
264 { "gpll", CLK_GENERAL },
265 #ifdef CONFIG_ROCKCHIP_RK3036
274 ret = rockchip_get_clk(&dev);
276 printf("clk-uclass not found\n");
280 for (i = 0; i < ARRAY_SIZE(clks); i++) {
285 ret = clk_request(dev, &clk);
289 rate = clk_get_rate(&clk);
290 printf("%s: %lu\n", clks[i].name, rate);
299 clock, 2, 1, do_clock,
300 "display information about clocks",
304 #define GRF_SOC_CON2 0xff77024c
306 int board_early_init_f(void)
308 struct udevice *pinctrl;
313 * This init is done in SPL, but when chain-loading U-Boot SPL will
314 * have been skipped. Allow the clock driver to check if it needs
317 ret = rockchip_get_clk(&dev);
319 debug("CLK init failed: %d\n", ret);
322 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
324 debug("%s: Cannot find pinctrl device\n", __func__);
328 /* Enable debug UART */
329 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
331 debug("%s: Failed to set up console UART\n", __func__);
334 rk_setreg(GRF_SOC_CON2, 1 << 0);