2 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
9 #include <debug_uart.h>
14 #include <asm/arch/bootrom.h>
15 #include <asm/arch/cru_rk3368.h>
16 #include <asm/arch/grf_rk3368.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/timer.h>
21 DECLARE_GLOBAL_DATA_PTR;
24 * The ARMv8 generic timer uses the STIMER1 as its clock-source.
25 * Set up the STIMER1 to free-running (i.e. auto-reload) to start
26 * the generic timer counting (if we don't do this, udelay will not
27 * work and block indefinitively).
29 static void secure_timer_init(void)
31 struct rk_timer * const stimer1 =
32 (struct rk_timer * const)0xff830020;
33 const u32 TIMER_EN = BIT(0);
35 writel(~0u, &stimer1->timer_load_count0);
36 writel(~0u, &stimer1->timer_load_count1);
37 writel(TIMER_EN, &stimer1->timer_ctrl_reg);
41 * The SPL (and also the full U-Boot stage on the RK3368) will run in
42 * secure mode (i.e. EL3) and an ATF will eventually be booted before
43 * starting up the operating system... so we can initialize the SGRF
44 * here and rely on the ATF installing the final (secure) policy
47 static inline uintptr_t sgrf_soc_con_addr(unsigned no)
49 const uintptr_t SGRF_BASE =
50 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
52 return SGRF_BASE + sizeof(u32) * no;
55 static inline uintptr_t sgrf_busdmac_addr(unsigned no)
57 const uintptr_t SGRF_BASE =
58 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
59 const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
60 const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
62 return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
65 static void sgrf_init(void)
67 struct rk3368_cru * const cru =
68 (struct rk3368_cru * const)rockchip_get_cru();
69 const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
70 const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
71 const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
73 /* Set all configurable IP to 'non secure'-mode */
74 rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
75 rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
76 rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
79 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
80 * Original comment: "ddr space set no secure mode"
82 rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
83 rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
84 rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
86 /* Set 'secure dma' to 'non secure'-mode */
87 rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
88 rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
92 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
93 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
98 rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
99 rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
102 void board_debug_uart_init(void)
105 * N.B.: This is called before the device-model has been
106 * initialised. For this reason, we can not access
107 * the GRF address range using the syscon API.
109 struct rk3368_grf * const grf =
110 (struct rk3368_grf * const)0xff770000;
113 GPIO2D1_MASK = GENMASK(3, 2),
115 GPIO2D1_UART0_SOUT = (1 << 2),
117 GPIO2D0_MASK = GENMASK(1, 0),
119 GPIO2D0_UART0_SIN = (1 << 0),
122 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
123 /* Enable early UART0 on the RK3368 */
124 rk_clrsetreg(&grf->gpio2d_iomux,
125 GPIO2D0_MASK, GPIO2D0_UART0_SIN);
126 rk_clrsetreg(&grf->gpio2d_iomux,
127 GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
131 void board_init_f(ulong dummy)
139 * Debug UART can be used from here if required:
144 * printascii("string");
147 printascii("U-Boot TPL board init\n");
150 ret = spl_early_init();
152 debug("spl_early_init() failed: %d\n", ret);
156 /* Make sure the ARMv8 generic timer counts */
158 /* Reset security, so we can use DMA in the MMC drivers */
161 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
163 debug("DRAM init failed: %d\n", ret);
168 void board_return_to_bootrom(void)
173 u32 spl_boot_device(void)
175 return BOOT_DEVICE_BOOTROM;