2 * (C) Copyright 2016-2017 Rockchip Inc.
4 * SPDX-License-Identifier: GPL-2.0
6 * Adapted from coreboot.
12 #include <dt-structs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sdram_rk3399.h>
19 #include <asm/arch/cru_rk3399.h>
20 #include <asm/arch/grf_rk3399.h>
21 #include <asm/arch/hardware.h>
22 #include <linux/err.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 struct rk3399_ddr_pctl_regs *pctl;
28 struct rk3399_ddr_pi_regs *pi;
29 struct rk3399_ddr_publ_regs *publ;
30 struct rk3399_msch_regs *msch;
34 #ifdef CONFIG_SPL_BUILD
35 struct chan_info chan[2];
37 struct rk3399_cru *cru;
38 struct rk3399_pmucru *pmucru;
39 struct rk3399_pmusgrf_regs *pmusgrf;
40 struct rk3399_ddr_cic_regs *cic;
43 struct rk3399_pmugrf_regs *pmugrf;
47 * sys_reg bitfield struct
68 #define SYS_REG_DDRTYPE_SHIFT 13
69 #define SYS_REG_DDRTYPE_MASK 7
70 #define SYS_REG_NUM_CH_SHIFT 12
71 #define SYS_REG_NUM_CH_MASK 1
72 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch))
73 #define SYS_REG_ROW_3_4_MASK 1
74 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch))
75 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16)
76 #define SYS_REG_RANK_MASK 1
77 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16)
78 #define SYS_REG_COL_MASK 3
79 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16)
80 #define SYS_REG_BK_MASK 1
81 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16)
82 #define SYS_REG_CS0_ROW_MASK 3
83 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16)
84 #define SYS_REG_CS1_ROW_MASK 3
85 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16)
86 #define SYS_REG_BW_MASK 3
87 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16)
88 #define SYS_REG_DBW_MASK 3
90 #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6))
91 #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
92 #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
94 #define PHY_DRV_ODT_Hi_Z 0x0
95 #define PHY_DRV_ODT_240 0x1
96 #define PHY_DRV_ODT_120 0x8
97 #define PHY_DRV_ODT_80 0x9
98 #define PHY_DRV_ODT_60 0xc
99 #define PHY_DRV_ODT_48 0xd
100 #define PHY_DRV_ODT_40 0xe
101 #define PHY_DRV_ODT_34_3 0xf
103 #ifdef CONFIG_SPL_BUILD
105 struct rockchip_dmc_plat {
106 #if CONFIG_IS_ENABLED(OF_PLATDATA)
107 struct dtd_rockchip_rk3399_dmc dtplat;
109 struct rk3399_sdram_params sdram_params;
114 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
118 for (i = 0; i < n / sizeof(u32); i++) {
125 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
128 u32 *denali_phy = ddr_publ_regs->denali_phy;
130 /* From IP spec, only freq small than 125 can enter dll bypass mode */
132 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
133 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
134 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
135 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
136 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
138 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
139 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
140 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
141 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
143 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
144 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
145 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
146 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
147 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
149 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
150 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
151 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
152 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
156 static void set_memory_map(const struct chan_info *chan, u32 channel,
157 const struct rk3399_sdram_params *sdram_params)
159 const struct rk3399_sdram_channel *sdram_ch =
160 &sdram_params->ch[channel];
161 u32 *denali_ctl = chan->pctl->denali_ctl;
162 u32 *denali_pi = chan->pi->denali_pi;
167 /* Get row number from ddrconfig setting */
168 if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4)
170 else if (sdram_ch->ddrconfig == 3)
175 cs_map = (sdram_ch->rank > 1) ? 3 : 1;
176 reduc = (sdram_ch->bw == 2) ? 0 : 1;
178 /* Set the dram configuration to ctrl */
179 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
180 clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
181 ((3 - sdram_ch->bk) << 16) |
184 clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
185 cs_map | (reduc << 16));
187 /* PI_199 PI_COL_DIFF:RW:0:4 */
188 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
190 /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
191 clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
192 ((3 - sdram_ch->bk) << 16) |
194 /* PI_41 PI_CS_MAP:RW:24:4 */
195 clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
196 if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3))
197 writel(0x2EC7FFFF, &denali_pi[34]);
200 static void set_ds_odt(const struct chan_info *chan,
201 const struct rk3399_sdram_params *sdram_params)
203 u32 *denali_phy = chan->publ->denali_phy;
205 u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
206 u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
207 u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
208 u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
211 if (sdram_params->base.dramtype == LPDDR4) {
212 tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
213 tsel_wr_select_p = PHY_DRV_ODT_40;
214 ca_tsel_wr_select_p = PHY_DRV_ODT_40;
215 tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
217 tsel_rd_select_n = PHY_DRV_ODT_240;
218 tsel_wr_select_n = PHY_DRV_ODT_40;
219 ca_tsel_wr_select_n = PHY_DRV_ODT_40;
220 tsel_idle_select_n = PHY_DRV_ODT_240;
221 } else if (sdram_params->base.dramtype == LPDDR3) {
222 tsel_rd_select_p = PHY_DRV_ODT_240;
223 tsel_wr_select_p = PHY_DRV_ODT_34_3;
224 ca_tsel_wr_select_p = PHY_DRV_ODT_48;
225 tsel_idle_select_p = PHY_DRV_ODT_240;
227 tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
228 tsel_wr_select_n = PHY_DRV_ODT_34_3;
229 ca_tsel_wr_select_n = PHY_DRV_ODT_48;
230 tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
232 tsel_rd_select_p = PHY_DRV_ODT_240;
233 tsel_wr_select_p = PHY_DRV_ODT_34_3;
234 ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
235 tsel_idle_select_p = PHY_DRV_ODT_240;
237 tsel_rd_select_n = PHY_DRV_ODT_240;
238 tsel_wr_select_n = PHY_DRV_ODT_34_3;
239 ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
240 tsel_idle_select_n = PHY_DRV_ODT_240;
243 if (sdram_params->base.odt == 1)
252 * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
253 * sets termination values for read/idle cycles and drive strength
254 * for write cycles for DQ/DM
256 reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
257 (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
258 (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
259 clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
260 clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
261 clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
262 clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
265 * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
266 * sets termination values for read/idle cycles and drive strength
267 * for write cycles for DQS
269 clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
270 clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
271 clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
272 clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
274 /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
275 reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4);
276 clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
277 clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
278 clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
280 /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
281 clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
283 /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
284 clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
286 /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
287 clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
289 /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
290 clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
292 /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
293 clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
295 /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
296 clrsetbits_le32(&denali_phy[924], 0xff,
297 tsel_wr_select_n | (tsel_wr_select_p << 4));
298 clrsetbits_le32(&denali_phy[925], 0xff,
299 tsel_rd_select_n | (tsel_rd_select_p << 4));
301 /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
302 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
304 clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
305 clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
306 clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
307 clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
309 /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
310 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
312 clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
313 clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
314 clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
315 clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
317 /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
318 reg_value = tsel_wr_en << 8;
319 clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
320 clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
321 clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
323 /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
324 reg_value = tsel_wr_en << 17;
325 clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
327 * pad_rst/cke/cs/clk_term tsel 1bits
328 * DENALI_PHY_938/936/940/934 offset_17
330 clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
331 clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
332 clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
333 clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
335 /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
336 clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
339 static int phy_io_config(const struct chan_info *chan,
340 const struct rk3399_sdram_params *sdram_params)
342 u32 *denali_phy = chan->publ->denali_phy;
343 u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
346 u32 drv_value, odt_value;
350 if (sdram_params->base.dramtype == LPDDR4) {
353 vref_value_dq = 0x1f;
355 vref_value_ac = 0x1f;
356 } else if (sdram_params->base.dramtype == LPDDR3) {
357 if (sdram_params->base.odt == 1) {
358 vref_mode_dq = 0x5; /* LPDDR3 ODT */
359 drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
360 odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
361 if (drv_value == PHY_DRV_ODT_48) {
363 case PHY_DRV_ODT_240:
364 vref_value_dq = 0x16;
366 case PHY_DRV_ODT_120:
367 vref_value_dq = 0x26;
370 vref_value_dq = 0x36;
373 debug("Invalid ODT value.\n");
376 } else if (drv_value == PHY_DRV_ODT_40) {
378 case PHY_DRV_ODT_240:
379 vref_value_dq = 0x19;
381 case PHY_DRV_ODT_120:
382 vref_value_dq = 0x23;
385 vref_value_dq = 0x31;
388 debug("Invalid ODT value.\n");
391 } else if (drv_value == PHY_DRV_ODT_34_3) {
393 case PHY_DRV_ODT_240:
394 vref_value_dq = 0x17;
396 case PHY_DRV_ODT_120:
397 vref_value_dq = 0x20;
400 vref_value_dq = 0x2e;
403 debug("Invalid ODT value.\n");
407 debug("Invalid DRV value.\n");
411 vref_mode_dq = 0x2; /* LPDDR3 */
412 vref_value_dq = 0x1f;
415 vref_value_ac = 0x1f;
416 } else if (sdram_params->base.dramtype == DDR3) {
419 vref_value_dq = 0x1f;
421 vref_value_ac = 0x1f;
423 debug("Unknown DRAM type.\n");
427 reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
429 /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
430 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
431 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
432 clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
433 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
434 clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
435 /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
436 clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
438 reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
440 /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
441 clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
443 if (sdram_params->base.dramtype == LPDDR4)
445 else if (sdram_params->base.dramtype == LPDDR3)
447 else if (sdram_params->base.dramtype == DDR3)
452 /* PHY_924 PHY_PAD_FDBK_DRIVE */
453 clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
454 /* PHY_926 PHY_PAD_DATA_DRIVE */
455 clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
456 /* PHY_927 PHY_PAD_DQS_DRIVE */
457 clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
458 /* PHY_928 PHY_PAD_ADDR_DRIVE */
459 clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
460 /* PHY_929 PHY_PAD_CLK_DRIVE */
461 clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
462 /* PHY_935 PHY_PAD_CKE_DRIVE */
463 clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
464 /* PHY_937 PHY_PAD_RST_DRIVE */
465 clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
466 /* PHY_939 PHY_PAD_CS_DRIVE */
467 clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
471 if (sdram_params->base.ddr_freq < 400)
473 else if (sdram_params->base.ddr_freq < 800)
475 else if (sdram_params->base.ddr_freq < 1200)
480 /* PHY_924 PHY_PAD_FDBK_DRIVE */
481 clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
482 /* PHY_926 PHY_PAD_DATA_DRIVE */
483 clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
484 /* PHY_927 PHY_PAD_DQS_DRIVE */
485 clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
486 /* PHY_928 PHY_PAD_ADDR_DRIVE */
487 clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
488 /* PHY_929 PHY_PAD_CLK_DRIVE */
489 clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
490 /* PHY_935 PHY_PAD_CKE_DRIVE */
491 clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
492 /* PHY_937 PHY_PAD_RST_DRIVE */
493 clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
494 /* PHY_939 PHY_PAD_CS_DRIVE */
495 clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
500 static int pctl_cfg(const struct chan_info *chan, u32 channel,
501 const struct rk3399_sdram_params *sdram_params)
503 u32 *denali_ctl = chan->pctl->denali_ctl;
504 u32 *denali_pi = chan->pi->denali_pi;
505 u32 *denali_phy = chan->publ->denali_phy;
506 const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl;
507 const u32 *params_phy = sdram_params->phy_regs.denali_phy;
509 u32 pwrup_srefresh_exit;
511 const ulong timeout_ms = 200;
514 * work around controller bug:
515 * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
517 copy_to_reg(&denali_ctl[1], ¶ms_ctl[1],
518 sizeof(struct rk3399_ddr_pctl_regs) - 4);
519 writel(params_ctl[0], &denali_ctl[0]);
520 copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],
521 sizeof(struct rk3399_ddr_pi_regs));
522 /* rank count need to set for init */
523 set_memory_map(chan, channel, sdram_params);
525 writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]);
526 writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
527 writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
529 pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
530 clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
533 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
535 setbits_le32(&denali_pi[0], START);
536 setbits_le32(&denali_ctl[0], START);
538 /* Wating for phy DLL lock */
540 tmp = readl(&denali_phy[920]);
541 tmp1 = readl(&denali_phy[921]);
542 tmp2 = readl(&denali_phy[922]);
543 if ((((tmp >> 16) & 0x1) == 0x1) &&
544 (((tmp1 >> 16) & 0x1) == 0x1) &&
545 (((tmp1 >> 0) & 0x1) == 0x1) &&
546 (((tmp2 >> 0) & 0x1) == 0x1))
550 copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4);
551 copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4);
552 copy_to_reg(&denali_phy[128], ¶ms_phy[128], (218 - 128 + 1) * 4);
553 copy_to_reg(&denali_phy[256], ¶ms_phy[256], (346 - 256 + 1) * 4);
554 copy_to_reg(&denali_phy[384], ¶ms_phy[384], (474 - 384 + 1) * 4);
555 copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4);
556 copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4);
557 copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4);
558 set_ds_odt(chan, sdram_params);
561 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
562 * dqs_tsel_wr_end[7:4] add Half cycle
564 tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
565 clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
566 tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
567 clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
568 tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
569 clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
570 tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
571 clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
574 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
575 * dq_tsel_wr_end[7:4] add Half cycle
577 tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
578 clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
579 tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
580 clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
581 tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
582 clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
583 tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
584 clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
586 ret = phy_io_config(chan, sdram_params);
591 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
593 /* Wating for PHY and DRAM init complete */
596 if (get_timer(tmp) > timeout_ms) {
597 error("DRAM (%s): phy failed to lock within %ld ms\n",
598 __func__, timeout_ms);
601 } while (!(readl(&denali_ctl[203]) & (1 << 3)));
602 debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
604 clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
605 pwrup_srefresh_exit);
609 static void select_per_cs_training_index(const struct chan_info *chan,
612 u32 *denali_phy = chan->publ->denali_phy;
614 /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
615 if ((readl(&denali_phy[84])>>16) & 1) {
618 * phy_per_cs_training_index_X 1bit offset_24
620 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
621 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
622 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
623 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
627 static void override_write_leveling_value(const struct chan_info *chan)
629 u32 *denali_ctl = chan->pctl->denali_ctl;
630 u32 *denali_phy = chan->publ->denali_phy;
633 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
634 setbits_le32(&denali_phy[896], 1);
638 * phy_per_cs_training_multicast_en_X 1bit offset_16
640 clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
641 clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
642 clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
643 clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
645 for (byte = 0; byte < 4; byte++)
646 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
649 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
650 clrbits_le32(&denali_phy[896], 1);
652 /* CTL_200 ctrlupd_req 1bit offset_8 */
653 clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
656 static int data_training_ca(const struct chan_info *chan, u32 channel,
657 const struct rk3399_sdram_params *sdram_params)
659 u32 *denali_pi = chan->pi->denali_pi;
660 u32 *denali_phy = chan->publ->denali_phy;
662 u32 obs_0, obs_1, obs_2, obs_err = 0;
663 u32 rank = sdram_params->ch[channel].rank;
665 for (i = 0; i < rank; i++) {
666 select_per_cs_training_index(chan, i);
667 /* PI_100 PI_CALVL_EN:RW:8:2 */
668 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
669 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
670 clrsetbits_le32(&denali_pi[92],
671 (0x1 << 16) | (0x3 << 24),
672 (0x1 << 16) | (i << 24));
674 /* Waiting for training complete */
676 /* PI_174 PI_INT_STATUS:RD:8:18 */
677 tmp = readl(&denali_pi[174]) >> 8;
680 * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
682 obs_0 = readl(&denali_phy[532]);
683 obs_1 = readl(&denali_phy[660]);
684 obs_2 = readl(&denali_phy[788]);
685 if (((obs_0 >> 30) & 0x3) ||
686 ((obs_1 >> 30) & 0x3) ||
687 ((obs_2 >> 30) & 0x3))
689 if ((((tmp >> 11) & 0x1) == 0x1) &&
690 (((tmp >> 13) & 0x1) == 0x1) &&
691 (((tmp >> 5) & 0x1) == 0x0) &&
694 else if ((((tmp >> 5) & 0x1) == 0x1) ||
698 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
699 writel(0x00003f7c, (&denali_pi[175]));
701 clrbits_le32(&denali_pi[100], 0x3 << 8);
706 static int data_training_wl(const struct chan_info *chan, u32 channel,
707 const struct rk3399_sdram_params *sdram_params)
709 u32 *denali_pi = chan->pi->denali_pi;
710 u32 *denali_phy = chan->publ->denali_phy;
712 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
713 u32 rank = sdram_params->ch[channel].rank;
715 for (i = 0; i < rank; i++) {
716 select_per_cs_training_index(chan, i);
717 /* PI_60 PI_WRLVL_EN:RW:8:2 */
718 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
719 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
720 clrsetbits_le32(&denali_pi[59],
721 (0x1 << 8) | (0x3 << 16),
722 (0x1 << 8) | (i << 16));
724 /* Waiting for training complete */
726 /* PI_174 PI_INT_STATUS:RD:8:18 */
727 tmp = readl(&denali_pi[174]) >> 8;
730 * check status obs, if error maybe can not
731 * get leveling done PHY_40/168/296/424
732 * phy_wrlvl_status_obs_X:0:13
734 obs_0 = readl(&denali_phy[40]);
735 obs_1 = readl(&denali_phy[168]);
736 obs_2 = readl(&denali_phy[296]);
737 obs_3 = readl(&denali_phy[424]);
738 if (((obs_0 >> 12) & 0x1) ||
739 ((obs_1 >> 12) & 0x1) ||
740 ((obs_2 >> 12) & 0x1) ||
741 ((obs_3 >> 12) & 0x1))
743 if ((((tmp >> 10) & 0x1) == 0x1) &&
744 (((tmp >> 13) & 0x1) == 0x1) &&
745 (((tmp >> 4) & 0x1) == 0x0) &&
748 else if ((((tmp >> 4) & 0x1) == 0x1) ||
752 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
753 writel(0x00003f7c, (&denali_pi[175]));
756 override_write_leveling_value(chan);
757 clrbits_le32(&denali_pi[60], 0x3 << 8);
762 static int data_training_rg(const struct chan_info *chan, u32 channel,
763 const struct rk3399_sdram_params *sdram_params)
765 u32 *denali_pi = chan->pi->denali_pi;
766 u32 *denali_phy = chan->publ->denali_phy;
768 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
769 u32 rank = sdram_params->ch[channel].rank;
771 for (i = 0; i < rank; i++) {
772 select_per_cs_training_index(chan, i);
773 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
774 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
776 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
777 * PI_RDLVL_CS:RW:24:2
779 clrsetbits_le32(&denali_pi[74],
780 (0x1 << 16) | (0x3 << 24),
781 (0x1 << 16) | (i << 24));
783 /* Waiting for training complete */
785 /* PI_174 PI_INT_STATUS:RD:8:18 */
786 tmp = readl(&denali_pi[174]) >> 8;
791 * PHY_GTLVL_STATUS_OBS_x:16:8
793 obs_0 = readl(&denali_phy[43]);
794 obs_1 = readl(&denali_phy[171]);
795 obs_2 = readl(&denali_phy[299]);
796 obs_3 = readl(&denali_phy[427]);
797 if (((obs_0 >> (16 + 6)) & 0x3) ||
798 ((obs_1 >> (16 + 6)) & 0x3) ||
799 ((obs_2 >> (16 + 6)) & 0x3) ||
800 ((obs_3 >> (16 + 6)) & 0x3))
802 if ((((tmp >> 9) & 0x1) == 0x1) &&
803 (((tmp >> 13) & 0x1) == 0x1) &&
804 (((tmp >> 3) & 0x1) == 0x0) &&
807 else if ((((tmp >> 3) & 0x1) == 0x1) ||
811 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
812 writel(0x00003f7c, (&denali_pi[175]));
814 clrbits_le32(&denali_pi[80], 0x3 << 24);
819 static int data_training_rl(const struct chan_info *chan, u32 channel,
820 const struct rk3399_sdram_params *sdram_params)
822 u32 *denali_pi = chan->pi->denali_pi;
824 u32 rank = sdram_params->ch[channel].rank;
826 for (i = 0; i < rank; i++) {
827 select_per_cs_training_index(chan, i);
828 /* PI_80 PI_RDLVL_EN:RW:16:2 */
829 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
830 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
831 clrsetbits_le32(&denali_pi[74],
832 (0x1 << 8) | (0x3 << 24),
833 (0x1 << 8) | (i << 24));
835 /* Waiting for training complete */
837 /* PI_174 PI_INT_STATUS:RD:8:18 */
838 tmp = readl(&denali_pi[174]) >> 8;
841 * make sure status obs not report error bit
843 * phy_rdlvl_status_obs_X:16:8
845 if ((((tmp >> 8) & 0x1) == 0x1) &&
846 (((tmp >> 13) & 0x1) == 0x1) &&
847 (((tmp >> 2) & 0x1) == 0x0))
849 else if (((tmp >> 2) & 0x1) == 0x1)
852 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
853 writel(0x00003f7c, (&denali_pi[175]));
855 clrbits_le32(&denali_pi[80], 0x3 << 16);
860 static int data_training_wdql(const struct chan_info *chan, u32 channel,
861 const struct rk3399_sdram_params *sdram_params)
863 u32 *denali_pi = chan->pi->denali_pi;
865 u32 rank = sdram_params->ch[channel].rank;
867 for (i = 0; i < rank; i++) {
868 select_per_cs_training_index(chan, i);
870 * disable PI_WDQLVL_VREF_EN before wdq leveling?
871 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
873 clrbits_le32(&denali_pi[181], 0x1 << 8);
874 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
875 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
876 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
877 clrsetbits_le32(&denali_pi[121],
878 (0x1 << 8) | (0x3 << 16),
879 (0x1 << 8) | (i << 16));
881 /* Waiting for training complete */
883 /* PI_174 PI_INT_STATUS:RD:8:18 */
884 tmp = readl(&denali_pi[174]) >> 8;
885 if ((((tmp >> 12) & 0x1) == 0x1) &&
886 (((tmp >> 13) & 0x1) == 0x1) &&
887 (((tmp >> 6) & 0x1) == 0x0))
889 else if (((tmp >> 6) & 0x1) == 0x1)
892 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
893 writel(0x00003f7c, (&denali_pi[175]));
895 clrbits_le32(&denali_pi[124], 0x3 << 16);
900 static int data_training(const struct chan_info *chan, u32 channel,
901 const struct rk3399_sdram_params *sdram_params,
904 u32 *denali_phy = chan->publ->denali_phy;
906 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
907 setbits_le32(&denali_phy[927], (1 << 22));
909 if (training_flag == PI_FULL_TRAINING) {
910 if (sdram_params->base.dramtype == LPDDR4) {
911 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
912 PI_READ_GATE_TRAINING |
913 PI_READ_LEVELING | PI_WDQ_LEVELING;
914 } else if (sdram_params->base.dramtype == LPDDR3) {
915 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
916 PI_READ_GATE_TRAINING;
917 } else if (sdram_params->base.dramtype == DDR3) {
918 training_flag = PI_WRITE_LEVELING |
919 PI_READ_GATE_TRAINING |
924 /* ca training(LPDDR4,LPDDR3 support) */
925 if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING)
926 data_training_ca(chan, channel, sdram_params);
928 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
929 if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING)
930 data_training_wl(chan, channel, sdram_params);
932 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
933 if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING)
934 data_training_rg(chan, channel, sdram_params);
936 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
937 if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING)
938 data_training_rl(chan, channel, sdram_params);
940 /* wdq leveling(LPDDR4 support) */
941 if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING)
942 data_training_wdql(chan, channel, sdram_params);
944 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
945 clrbits_le32(&denali_phy[927], (1 << 22));
950 static void set_ddrconfig(const struct chan_info *chan,
951 const struct rk3399_sdram_params *sdram_params,
952 unsigned char channel, u32 ddrconfig)
954 /* only need to set ddrconfig */
955 struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
956 unsigned int cs0_cap = 0;
957 unsigned int cs1_cap = 0;
959 cs0_cap = (1 << (sdram_params->ch[channel].cs0_row
960 + sdram_params->ch[channel].col
961 + sdram_params->ch[channel].bk
962 + sdram_params->ch[channel].bw - 20));
963 if (sdram_params->ch[channel].rank > 1)
964 cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row
965 - sdram_params->ch[channel].cs1_row);
966 if (sdram_params->ch[channel].row_3_4) {
967 cs0_cap = cs0_cap * 3 / 4;
968 cs1_cap = cs1_cap * 3 / 4;
971 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
972 writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
973 &ddr_msch_regs->ddrsize);
976 static void dram_all_config(struct dram_info *dram,
977 const struct rk3399_sdram_params *sdram_params)
980 unsigned int channel, idx;
982 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
983 sys_reg |= (sdram_params->base.num_channels - 1)
984 << SYS_REG_NUM_CH_SHIFT;
985 for (channel = 0, idx = 0;
986 (idx < sdram_params->base.num_channels) && (channel < 2);
988 const struct rk3399_sdram_channel *info =
989 &sdram_params->ch[channel];
990 struct rk3399_msch_regs *ddr_msch_regs;
991 const struct rk3399_msch_timings *noc_timing;
993 if (sdram_params->ch[channel].col == 0)
996 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel);
997 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
998 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
999 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
1000 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
1001 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel);
1002 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel);
1003 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
1004 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
1006 ddr_msch_regs = dram->chan[channel].msch;
1007 noc_timing = &sdram_params->ch[channel].noc_timings;
1008 writel(noc_timing->ddrtiminga0,
1009 &ddr_msch_regs->ddrtiminga0);
1010 writel(noc_timing->ddrtimingb0,
1011 &ddr_msch_regs->ddrtimingb0);
1012 writel(noc_timing->ddrtimingc0,
1013 &ddr_msch_regs->ddrtimingc0);
1014 writel(noc_timing->devtodev0,
1015 &ddr_msch_regs->devtodev0);
1016 writel(noc_timing->ddrmode,
1017 &ddr_msch_regs->ddrmode);
1019 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
1020 if (sdram_params->ch[channel].rank == 1)
1021 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1025 writel(sys_reg, &dram->pmugrf->os_reg2);
1026 rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1027 sdram_params->base.stride << 10);
1029 /* reboot hold register set */
1030 writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1031 PRESET_GPIO1_HOLD(1),
1032 &dram->pmucru->pmucru_rstnhold_con[1]);
1033 clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1036 static int switch_to_phy_index1(struct dram_info *dram,
1037 const struct rk3399_sdram_params *sdram_params)
1041 u32 ch_count = sdram_params->base.num_channels;
1045 writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1046 1 << 4 | 1 << 2 | 1),
1047 &dram->cic->cic_ctrl0);
1048 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1052 debug("index1 frequency change overtime\n");
1058 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1059 while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1062 debug("index1 frequency done overtime\n");
1067 for (channel = 0; channel < ch_count; channel++) {
1068 denali_phy = dram->chan[channel].publ->denali_phy;
1069 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1070 ret = data_training(&dram->chan[channel], channel,
1071 sdram_params, PI_FULL_TRAINING);
1073 debug("index1 training failed\n");
1081 static int sdram_init(struct dram_info *dram,
1082 const struct rk3399_sdram_params *sdram_params)
1084 unsigned char dramtype = sdram_params->base.dramtype;
1085 unsigned int ddr_freq = sdram_params->base.ddr_freq;
1088 debug("Starting SDRAM initialization...\n");
1090 if ((dramtype == DDR3 && ddr_freq > 933) ||
1091 (dramtype == LPDDR3 && ddr_freq > 933) ||
1092 (dramtype == LPDDR4 && ddr_freq > 800)) {
1093 debug("SDRAM frequency is to high!");
1097 for (channel = 0; channel < 2; channel++) {
1098 const struct chan_info *chan = &dram->chan[channel];
1099 struct rk3399_ddr_publ_regs *publ = chan->publ;
1101 phy_dll_bypass_set(publ, ddr_freq);
1103 if (channel >= sdram_params->base.num_channels)
1106 if (pctl_cfg(chan, channel, sdram_params) != 0) {
1107 printf("pctl_cfg fail, reset\n");
1111 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1112 if (dramtype == LPDDR3)
1115 if (data_training(chan, channel,
1116 sdram_params, PI_FULL_TRAINING)) {
1117 printf("SDRAM initialization failed, reset\n");
1121 set_ddrconfig(chan, sdram_params, channel,
1122 sdram_params->ch[channel].ddrconfig);
1124 dram_all_config(dram, sdram_params);
1125 switch_to_phy_index1(dram, sdram_params);
1127 debug("Finish SDRAM initialization...\n");
1131 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1133 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1134 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1137 ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1138 (u32 *)&plat->sdram_params,
1139 sizeof(plat->sdram_params) / sizeof(u32));
1141 printf("%s: Cannot read rockchip,sdram-params %d\n",
1145 ret = regmap_init_mem(dev, &plat->map);
1147 printf("%s: regmap failed %d\n", __func__, ret);
1153 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1154 static int conv_of_platdata(struct udevice *dev)
1156 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1157 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1160 ret = regmap_init_mem_platdata(dev, dtplat->reg,
1161 ARRAY_SIZE(dtplat->reg) / 4,
1170 static int rk3399_dmc_init(struct udevice *dev)
1172 struct dram_info *priv = dev_get_priv(dev);
1173 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1175 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1176 struct rk3399_sdram_params *params = &plat->sdram_params;
1178 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1179 struct rk3399_sdram_params *params =
1180 (void *)dtplat->rockchip_sdram_params;
1182 ret = conv_of_platdata(dev);
1187 priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1188 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1189 priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1190 priv->pmucru = rockchip_get_pmucru();
1191 priv->cru = rockchip_get_cru();
1192 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1193 priv->chan[0].pi = regmap_get_range(plat->map, 1);
1194 priv->chan[0].publ = regmap_get_range(plat->map, 2);
1195 priv->chan[0].msch = regmap_get_range(plat->map, 3);
1196 priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1197 priv->chan[1].pi = regmap_get_range(plat->map, 5);
1198 priv->chan[1].publ = regmap_get_range(plat->map, 6);
1199 priv->chan[1].msch = regmap_get_range(plat->map, 7);
1201 debug("con reg %p %p %p %p %p %p %p %p\n",
1202 priv->chan[0].pctl, priv->chan[0].pi,
1203 priv->chan[0].publ, priv->chan[0].msch,
1204 priv->chan[1].pctl, priv->chan[1].pi,
1205 priv->chan[1].publ, priv->chan[1].msch);
1206 debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1207 priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1208 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1209 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1211 ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1214 printf("%s clk get failed %d\n", __func__, ret);
1217 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1219 printf("%s clk set failed %d\n", __func__, ret);
1222 ret = sdram_init(priv, params);
1224 printf("%s DRAM init failed%d\n", __func__, ret);
1232 size_t sdram_size_mb(struct dram_info *dram)
1234 u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
1235 size_t chipsize_mb = 0;
1239 u32 sys_reg = readl(&dram->pmugrf->os_reg2);
1240 u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT)
1241 & SYS_REG_NUM_CH_MASK);
1243 for (ch = 0; ch < ch_num; ch++) {
1244 rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
1246 col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
1247 bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
1248 cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
1249 SYS_REG_CS0_ROW_MASK);
1250 cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
1251 SYS_REG_CS1_ROW_MASK);
1252 bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
1254 row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
1255 SYS_REG_ROW_3_4_MASK;
1257 chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
1260 chipsize_mb += chipsize_mb >> (cs0_row - cs1_row);
1262 chipsize_mb = chipsize_mb * 3 / 4;
1263 size_mb += chipsize_mb;
1267 * we use the 0x00000000~0xf7ffffff space
1268 * since 0xf8000000~0xffffffff is soc register space
1271 size_mb = min_t(size_t, size_mb, 0xf8000000/(1<<20));
1276 static int rk3399_dmc_probe(struct udevice *dev)
1278 #ifdef CONFIG_SPL_BUILD
1279 if (rk3399_dmc_init(dev))
1282 struct dram_info *priv = dev_get_priv(dev);
1284 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1285 debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
1286 priv->info.base = 0;
1287 priv->info.size = sdram_size_mb(priv) << 20;
1292 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1294 struct dram_info *priv = dev_get_priv(dev);
1301 static struct ram_ops rk3399_dmc_ops = {
1302 .get_info = rk3399_dmc_get_info,
1306 static const struct udevice_id rk3399_dmc_ids[] = {
1307 { .compatible = "rockchip,rk3399-dmc" },
1311 U_BOOT_DRIVER(dmc_rk3399) = {
1312 .name = "rockchip_rk3399_dmc",
1314 .of_match = rk3399_dmc_ids,
1315 .ops = &rk3399_dmc_ops,
1316 #ifdef CONFIG_SPL_BUILD
1317 .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1319 .probe = rk3399_dmc_probe,
1320 .priv_auto_alloc_size = sizeof(struct dram_info),
1321 #ifdef CONFIG_SPL_BUILD
1322 .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),