2 * Clock drivers for Qualcomm APQ8016, APQ8096
4 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 * Based on Little Kernel driver, simplified
8 * SPDX-License-Identifier: BSD-3-Clause
12 #include <clk-uclass.h>
16 #include <linux/bitops.h>
17 #include "clock-snapdragon.h"
19 /* CBCR register fields */
20 #define CBCR_BRANCH_ENABLE_BIT BIT(0)
21 #define CBCR_BRANCH_OFF_BIT BIT(31)
23 extern ulong msm_set_rate(struct clk *clk, ulong rate);
25 /* Enable clock controlled by CBC soft macro */
26 void clk_enable_cbc(phys_addr_t cbcr)
28 setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
30 while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
34 void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0)
36 if (readl(base + gpll0->status) & gpll0->status_bit)
37 return; /* clock already enabled */
39 setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit);
41 while ((readl(base + gpll0->status) & gpll0->status_bit) == 0)
45 #define APPS_CMD_RGCR_UPDATE BIT(0)
47 /* Update clock command via CMD_RGCR */
48 void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
50 setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
52 /* Wait for frequency to be updated. */
53 while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
57 #define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
59 #define CFG_MASK 0x3FFF
61 #define CFG_DIVIDER_MASK 0x1F
63 /* root set rate for clocks with half integer and MND divider */
64 void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
65 int div, int m, int n, int source)
68 /* M value for MND divider. */
70 /* NOT(N-M) value for MND divider. */
71 u32 n_val = ~((n) - (m)) * !!(n);
72 /* NOT 2D value for MND divider. */
75 /* Program MND values */
76 writel(m_val, base + regs->M);
77 writel(n_val, base + regs->N);
78 writel(d_val, base + regs->D);
80 /* setup src select and divider */
81 cfg = readl(base + regs->cfg_rcgr);
83 cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
85 /* Set the divider; HW permits fraction dividers (+0.5), but
86 for simplicity, we will support integers only */
88 cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
91 cfg |= CFG_MODE_DUAL_EDGE;
93 writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
95 /* Inform h/w to start using the new config. */
96 clk_bcr_update(base + regs->cmd_rcgr);
99 static int msm_clk_probe(struct udevice *dev)
101 struct msm_clk_priv *priv = dev_get_priv(dev);
103 priv->base = devfdt_get_addr(dev);
104 if (priv->base == FDT_ADDR_T_NONE)
110 static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
112 return msm_set_rate(clk, rate);
115 static struct clk_ops msm_clk_ops = {
116 .set_rate = msm_clk_set_rate,
119 static const struct udevice_id msm_clk_ids[] = {
120 { .compatible = "qcom,gcc-msm8916" },
121 { .compatible = "qcom,gcc-apq8016" },
122 { .compatible = "qcom,gcc-msm8996" },
123 { .compatible = "qcom,gcc-apq8096" },
127 U_BOOT_DRIVER(clk_msm) = {
130 .of_match = msm_clk_ids,
132 .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
133 .probe = msm_clk_probe,