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Merge branch 'master' of git://git.denx.de/u-boot
[u-boot] / arch / arm / mach-socfpga / Kconfig
1 if ARCH_SOCFPGA
2
3 config TARGET_SOCFPGA_ARRIA5
4         bool
5
6 config TARGET_SOCFPGA_CYCLONE5
7         bool
8
9 choice
10         prompt "Altera SOCFPGA board select"
11         optional
12
13 config TARGET_SOCFPGA_ARRIA5_SOCDK
14         bool "Altera SOCFPGA SoCDK (Arria V)"
15         select TARGET_SOCFPGA_ARRIA5
16
17 config TARGET_SOCFPGA_CYCLONE5_SOCDK
18         bool "Altera SOCFPGA SoCDK (Cyclone V)"
19         select TARGET_SOCFPGA_CYCLONE5
20
21 config TARGET_SOCFPGA_DENX_MCVEVK
22         bool "DENX MCVEVK (Cyclone V)"
23         select TARGET_SOCFPGA_CYCLONE5
24
25 config TARGET_SOCFPGA_TERASIC_DE0_NANO
26         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
27         select TARGET_SOCFPGA_CYCLONE5
28
29 config TARGET_SOCFPGA_TERASIC_SOCKIT
30         bool "Terasic SoCkit (Cyclone V)"
31         select TARGET_SOCFPGA_CYCLONE5
32
33 endchoice
34
35 config SYS_BOARD
36         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
37         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
38         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
39         default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
40         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
41
42 config SYS_VENDOR
43         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
44         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
45         default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
46         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
47         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
48
49 config SYS_SOC
50         default "socfpga"
51
52 config SYS_CONFIG_NAME
53         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
54         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
55         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
56         default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
57         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
58
59 endif