3 config SPL_LIBCOMMON_SUPPORT
6 config SPL_LIBDISK_SUPPORT
9 config SPL_LIBGENERIC_SUPPORT
12 config SPL_MMC_SUPPORT
15 config SPL_NAND_SUPPORT
16 default y if SPL_NAND_DENALI
18 config SPL_SERIAL_SUPPORT
21 config SPL_SPI_FLASH_SUPPORT
22 default y if SPL_SPI_SUPPORT
24 config SPL_SPI_SUPPORT
27 config SPL_WATCHDOG_SUPPORT
30 config TARGET_SOCFPGA_ARRIA5
32 select TARGET_SOCFPGA_GEN5
34 config TARGET_SOCFPGA_CYCLONE5
36 select TARGET_SOCFPGA_GEN5
38 config TARGET_SOCFPGA_GEN5
42 prompt "Altera SOCFPGA board select"
45 config TARGET_SOCFPGA_ARRIA5_SOCDK
46 bool "Altera SOCFPGA SoCDK (Arria V)"
47 select TARGET_SOCFPGA_ARRIA5
49 config TARGET_SOCFPGA_CYCLONE5_SOCDK
50 bool "Altera SOCFPGA SoCDK (Cyclone V)"
51 select TARGET_SOCFPGA_CYCLONE5
53 config TARGET_SOCFPGA_DENX_MCVEVK
54 bool "DENX MCVEVK (Cyclone V)"
55 select TARGET_SOCFPGA_CYCLONE5
57 config TARGET_SOCFPGA_EBV_SOCRATES
58 bool "EBV SoCrates (Cyclone V)"
59 select TARGET_SOCFPGA_CYCLONE5
61 config TARGET_SOCFPGA_IS1
62 bool "IS1 (Cyclone V)"
63 select TARGET_SOCFPGA_CYCLONE5
65 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
66 bool "samtec VIN|ING FPGA (Cyclone V)"
67 select TARGET_SOCFPGA_CYCLONE5
69 config TARGET_SOCFPGA_SR1500
70 bool "SR1500 (Cyclone V)"
71 select TARGET_SOCFPGA_CYCLONE5
73 config TARGET_SOCFPGA_TERASIC_DE0_NANO
74 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
75 select TARGET_SOCFPGA_CYCLONE5
77 config TARGET_SOCFPGA_TERASIC_SOCKIT
78 bool "Terasic SoCkit (Cyclone V)"
79 select TARGET_SOCFPGA_CYCLONE5
84 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
85 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
86 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
87 default "is1" if TARGET_SOCFPGA_IS1
88 default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
89 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
90 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
91 default "sr1500" if TARGET_SOCFPGA_SR1500
92 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
95 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
96 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
97 default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
98 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
99 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
100 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
101 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
106 config SYS_CONFIG_NAME
107 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
108 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
109 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
110 default "socfpga_is1" if TARGET_SOCFPGA_IS1
111 default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
112 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
113 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
114 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
115 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA