3 config SPL_LIBCOMMON_SUPPORT
6 config SPL_LIBDISK_SUPPORT
9 config SPL_LIBGENERIC_SUPPORT
12 config SPL_MMC_SUPPORT
15 config SPL_NAND_SUPPORT
16 default y if SPL_NAND_DENALI
18 config SPL_SERIAL_SUPPORT
21 config SPL_SPI_FLASH_SUPPORT
22 default y if SPL_SPI_SUPPORT
24 config SPL_SPI_SUPPORT
27 config SPL_WATCHDOG_SUPPORT
30 config TARGET_SOCFPGA_ARRIA5
32 select TARGET_SOCFPGA_GEN5
34 config TARGET_SOCFPGA_CYCLONE5
36 select TARGET_SOCFPGA_GEN5
38 config TARGET_SOCFPGA_GEN5
42 prompt "Altera SOCFPGA board select"
45 config TARGET_SOCFPGA_ARRIA5_SOCDK
46 bool "Altera SOCFPGA SoCDK (Arria V)"
47 select TARGET_SOCFPGA_ARRIA5
49 config TARGET_SOCFPGA_CYCLONE5_SOCDK
50 bool "Altera SOCFPGA SoCDK (Cyclone V)"
51 select TARGET_SOCFPGA_CYCLONE5
53 config TARGET_SOCFPGA_DENX_MCVEVK
54 bool "DENX MCVEVK (Cyclone V)"
55 select TARGET_SOCFPGA_CYCLONE5
57 config TARGET_SOCFPGA_EBV_SOCRATES
58 bool "EBV SoCrates (Cyclone V)"
59 select TARGET_SOCFPGA_CYCLONE5
61 config TARGET_SOCFPGA_IS1
62 bool "IS1 (Cyclone V)"
63 select TARGET_SOCFPGA_CYCLONE5
65 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
66 bool "samtec VIN|ING FPGA (Cyclone V)"
67 select BOARD_LATE_INIT
68 select TARGET_SOCFPGA_CYCLONE5
70 config TARGET_SOCFPGA_SR1500
71 bool "SR1500 (Cyclone V)"
72 select TARGET_SOCFPGA_CYCLONE5
74 config TARGET_SOCFPGA_TERASIC_DE0_NANO
75 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
76 select TARGET_SOCFPGA_CYCLONE5
78 config TARGET_SOCFPGA_TERASIC_DE1_SOC
79 bool "Terasic DE1-SoC (Cyclone V)"
80 select TARGET_SOCFPGA_CYCLONE5
82 config TARGET_SOCFPGA_TERASIC_SOCKIT
83 bool "Terasic SoCkit (Cyclone V)"
84 select TARGET_SOCFPGA_CYCLONE5
89 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
90 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
91 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
92 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
93 default "is1" if TARGET_SOCFPGA_IS1
94 default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
95 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
96 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
97 default "sr1500" if TARGET_SOCFPGA_SR1500
98 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
101 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
102 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
103 default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
104 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
105 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
106 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
107 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
108 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
113 config SYS_CONFIG_NAME
114 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
115 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
116 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
117 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
118 default "socfpga_is1" if TARGET_SOCFPGA_IS1
119 default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
120 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
121 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
122 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
123 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA