1 // SPDX-License-Identifier: GPL-2.0+
3 * Altera SoCFPGA common board code
5 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
11 #include <asm/arch/reset_manager.h>
12 #include <asm/arch/clock_manager.h>
13 #include <asm/arch/misc.h>
17 #include <usb/dwc2_udc.h>
19 DECLARE_GLOBAL_DATA_PTR;
24 * Miscellaneous platform dependent initialisations
28 /* Address of boot parameters for ATAG (if ATAG is used) */
29 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
31 #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
32 /* configuring the clock based on handoff */
33 cm_basic_init(gd->fdt_blob);
35 /* Add device descriptor to FPGA device table */
42 int dram_init_banksize(void)
44 fdtdec_setup_memory_banksize();
49 #ifdef CONFIG_USB_GADGET
50 struct dwc2_plat_otg_data socfpga_otg_data = {
51 .usb_gusbcfg = 0x1417,
54 int board_usb_init(int index, enum usb_init_type init)
59 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
60 COMPAT_ALTERA_SOCFPGA_DWC2USB,
62 if (count <= 0) /* No controller found. */
65 addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
66 if (addr == FDT_ADDR_T_NONE) {
67 printf("UDC Controller has no 'reg' property!\n");
71 /* Patch the address from OF into the controller pdata. */
72 socfpga_otg_data.regs_otg = addr;
74 return dwc2_udc_probe(&socfpga_otg_data);
77 int g_dnl_board_usb_cable_connected(void)