2 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock_manager.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 static const struct socfpga_clock_manager *clock_manager_base =
15 (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
18 * function to write the bypass register which requires a poll of the
21 static void cm_write_bypass(u32 val)
23 writel(val, &clock_manager_base->bypass);
27 /* function to write the ctrl register which requires a poll of the busy bit */
28 static void cm_write_ctrl(u32 val)
30 writel(val, &clock_manager_base->ctrl);
34 /* function to write a clock register that has phase information */
35 static int cm_write_with_phase(u32 value, u32 reg_address, u32 mask)
39 /* poll until phase is zero */
40 ret = wait_for_bit(__func__, (const u32 *)reg_address, mask,
45 writel(value, reg_address);
47 return wait_for_bit(__func__, (const u32 *)reg_address, mask,
52 * Setup clocks while making no assumptions about previous state of the clocks.
54 * Start by being paranoid and gate all sw managed clocks
55 * Put all plls in bypass
56 * Put all plls VCO registers back to reset value (bandgap power down).
57 * Put peripheral and main pll src to reset value to avoid glitch.
59 * Deassert bandgap power down and set numerator and denominator
61 * set internal dividers
62 * Wait for 7 us timer.
64 * Set external dividers while plls are locking
66 * Assert/deassert outreset all.
67 * Take all pll's out of bypass
69 * set source main and peripheral clocks
73 int cm_basic_init(const struct cm_config * const cfg)
78 /* Start by being paranoid and gate all sw managed clocks */
81 * We need to disable nandclk
82 * and then do another apb access before disabling
83 * gatting off the rest of the periperal clocks.
85 writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
86 readl(&clock_manager_base->per_pll.en),
87 &clock_manager_base->per_pll.en);
89 /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
90 writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
91 CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
92 CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
93 CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
94 CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
95 CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
96 &clock_manager_base->main_pll.en);
98 writel(0, &clock_manager_base->sdr_pll.en);
100 /* now we can gate off the rest of the peripheral clocks */
101 writel(0, &clock_manager_base->per_pll.en);
103 /* Put all plls in bypass */
104 cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
105 CLKMGR_BYPASS_MAINPLL);
107 /* Put all plls VCO registers back to reset value. */
108 writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
109 ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
110 &clock_manager_base->main_pll.vco);
111 writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
112 ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
113 &clock_manager_base->per_pll.vco);
114 writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
115 ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
116 &clock_manager_base->sdr_pll.vco);
119 * The clocks to the flash devices and the L4_MAIN clocks can
120 * glitch when coming out of safe mode if their source values
121 * are different from their reset value. So the trick it to
122 * put them back to their reset state, and change input
123 * after exiting safe mode but before ungating the clocks.
125 writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
126 &clock_manager_base->per_pll.src);
127 writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
128 &clock_manager_base->main_pll.l4src);
130 /* read back for the required 5 us delay. */
131 readl(&clock_manager_base->main_pll.vco);
132 readl(&clock_manager_base->per_pll.vco);
133 readl(&clock_manager_base->sdr_pll.vco);
137 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
138 * with numerator and denominator.
140 writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
141 writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
142 writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
145 * Time starts here. Must wait 7 us from
146 * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
148 end = timer_get_us() + 7;
151 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
153 /* altera group mpuclk */
154 writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
156 /* main main clock */
157 writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
160 writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
162 /* main for cfgs2fuser0clk */
163 writel(cfg->cfg2fuser0clk,
164 &clock_manager_base->main_pll.cfgs2fuser0clk);
166 /* Peri emac0 50 MHz default to RMII */
167 writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
169 /* Peri emac1 50 MHz default to RMII */
170 writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
173 writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
175 writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
177 /* Peri pernandsdmmcclk */
178 writel(cfg->mainnandsdmmcclk,
179 &clock_manager_base->main_pll.mainnandsdmmcclk);
181 writel(cfg->pernandsdmmcclk,
182 &clock_manager_base->per_pll.pernandsdmmcclk);
184 /* Peri perbaseclk */
185 writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
187 /* Peri s2fuser1clk */
188 writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
190 /* 7 us must have elapsed before we can enable the VCO */
191 while (timer_get_us() < end)
196 writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
197 &clock_manager_base->main_pll.vco);
200 writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
201 &clock_manager_base->per_pll.vco);
204 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
205 &clock_manager_base->sdr_pll.vco);
207 /* L3 MP and L3 SP */
208 writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
210 writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
212 writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
214 /* L4 MP, L4 SP, can0, and can1 */
215 writel(cfg->perdiv, &clock_manager_base->per_pll.div);
217 writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
219 cm_wait_for_lock(LOCKED_MASK);
221 /* write the sdram clock counters before toggling outreset all */
222 writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
223 &clock_manager_base->sdr_pll.ddrdqsclk);
225 writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
226 &clock_manager_base->sdr_pll.ddr2xdqsclk);
228 writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
229 &clock_manager_base->sdr_pll.ddrdqclk);
231 writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
232 &clock_manager_base->sdr_pll.s2fuser2clk);
235 * after locking, but before taking out of bypass
236 * assert/deassert outresetall
238 u32 mainvco = readl(&clock_manager_base->main_pll.vco);
240 /* assert main outresetall */
241 writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
242 &clock_manager_base->main_pll.vco);
244 u32 periphvco = readl(&clock_manager_base->per_pll.vco);
246 /* assert pheriph outresetall */
247 writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
248 &clock_manager_base->per_pll.vco);
250 /* assert sdram outresetall */
251 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
252 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
253 &clock_manager_base->sdr_pll.vco);
255 /* deassert main outresetall */
256 writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
257 &clock_manager_base->main_pll.vco);
259 /* deassert pheriph outresetall */
260 writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
261 &clock_manager_base->per_pll.vco);
263 /* deassert sdram outresetall */
264 writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
265 &clock_manager_base->sdr_pll.vco);
268 * now that we've toggled outreset all, all the clocks
269 * are aligned nicely; so we can change any phase.
271 ret = cm_write_with_phase(cfg->ddrdqsclk,
272 (u32)&clock_manager_base->sdr_pll.ddrdqsclk,
273 CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
277 /* SDRAM DDR2XDQSCLK */
278 ret = cm_write_with_phase(cfg->ddr2xdqsclk,
279 (u32)&clock_manager_base->sdr_pll.ddr2xdqsclk,
280 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
284 ret = cm_write_with_phase(cfg->ddrdqclk,
285 (u32)&clock_manager_base->sdr_pll.ddrdqclk,
286 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
290 ret = cm_write_with_phase(cfg->s2fuser2clk,
291 (u32)&clock_manager_base->sdr_pll.s2fuser2clk,
292 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
296 /* Take all three PLLs out of bypass when safe mode is cleared. */
299 /* clear safe mode */
300 cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
303 * now that safe mode is clear with clocks gated
304 * it safe to change the source mux for the flashes the the L4_MAIN
306 writel(cfg->persrc, &clock_manager_base->per_pll.src);
307 writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
309 /* Now ungate non-hw-managed clocks */
310 writel(~0, &clock_manager_base->main_pll.en);
311 writel(~0, &clock_manager_base->per_pll.en);
312 writel(~0, &clock_manager_base->sdr_pll.en);
314 /* Clear the loss of lock bits (write 1 to clear) */
315 writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
316 CLKMGR_INTER_MAINPLLLOST_MASK,
317 &clock_manager_base->inter);
322 static unsigned int cm_get_main_vco_clk_hz(void)
326 /* get the main VCO clock */
327 reg = readl(&clock_manager_base->main_pll.vco);
328 clock = cm_get_osc_clk_hz(1);
329 clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
330 CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
331 clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
332 CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1;
337 static unsigned int cm_get_per_vco_clk_hz(void)
341 /* identify PER PLL clock source */
342 reg = readl(&clock_manager_base->per_pll.vco);
343 reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
344 CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
345 if (reg == CLKMGR_VCO_SSRC_EOSC1)
346 clock = cm_get_osc_clk_hz(1);
347 else if (reg == CLKMGR_VCO_SSRC_EOSC2)
348 clock = cm_get_osc_clk_hz(2);
349 else if (reg == CLKMGR_VCO_SSRC_F2S)
350 clock = cm_get_f2s_per_ref_clk_hz();
352 /* get the PER VCO clock */
353 reg = readl(&clock_manager_base->per_pll.vco);
354 clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
355 CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
356 clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
357 CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1;
362 unsigned long cm_get_mpu_clk_hz(void)
366 clock = cm_get_main_vco_clk_hz();
368 /* get the MPU clock */
369 reg = readl(&clock_manager_base->altera.mpuclk);
371 reg = readl(&clock_manager_base->main_pll.mpuclk);
376 unsigned long cm_get_sdram_clk_hz(void)
380 /* identify SDRAM PLL clock source */
381 reg = readl(&clock_manager_base->sdr_pll.vco);
382 reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
383 CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
384 if (reg == CLKMGR_VCO_SSRC_EOSC1)
385 clock = cm_get_osc_clk_hz(1);
386 else if (reg == CLKMGR_VCO_SSRC_EOSC2)
387 clock = cm_get_osc_clk_hz(2);
388 else if (reg == CLKMGR_VCO_SSRC_F2S)
389 clock = cm_get_f2s_sdr_ref_clk_hz();
391 /* get the SDRAM VCO clock */
392 reg = readl(&clock_manager_base->sdr_pll.vco);
393 clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
394 CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
395 clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
396 CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
398 /* get the SDRAM (DDR_DQS) clock */
399 reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
400 reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
401 CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
407 unsigned int cm_get_l4_sp_clk_hz(void)
411 /* identify the source of L4 SP clock */
412 reg = readl(&clock_manager_base->main_pll.l4src);
413 reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
414 CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
416 if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
417 clock = cm_get_main_vco_clk_hz();
419 /* get the clock prior L4 SP divider (main clk) */
420 reg = readl(&clock_manager_base->altera.mainclk);
422 reg = readl(&clock_manager_base->main_pll.mainclk);
424 } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
425 clock = cm_get_per_vco_clk_hz();
427 /* get the clock prior L4 SP divider (periph_base_clk) */
428 reg = readl(&clock_manager_base->per_pll.perbaseclk);
432 /* get the L4 SP clock which supplied to UART */
433 reg = readl(&clock_manager_base->main_pll.maindiv);
434 reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
435 CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
436 clock = clock / (1 << reg);
441 unsigned int cm_get_mmc_controller_clk_hz(void)
445 /* identify the source of MMC clock */
446 reg = readl(&clock_manager_base->per_pll.src);
447 reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
448 CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
450 if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
451 clock = cm_get_f2s_per_ref_clk_hz();
452 } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
453 clock = cm_get_main_vco_clk_hz();
455 /* get the SDMMC clock */
456 reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
458 } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
459 clock = cm_get_per_vco_clk_hz();
461 /* get the SDMMC clock */
462 reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
466 /* further divide by 4 as we have fixed divider at wrapper */
471 unsigned int cm_get_qspi_controller_clk_hz(void)
475 /* identify the source of QSPI clock */
476 reg = readl(&clock_manager_base->per_pll.src);
477 reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
478 CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
480 if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
481 clock = cm_get_f2s_per_ref_clk_hz();
482 } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
483 clock = cm_get_main_vco_clk_hz();
485 /* get the qspi clock */
486 reg = readl(&clock_manager_base->main_pll.mainqspiclk);
488 } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
489 clock = cm_get_per_vco_clk_hz();
491 /* get the qspi clock */
492 reg = readl(&clock_manager_base->per_pll.perqspiclk);
499 unsigned int cm_get_spi_controller_clk_hz(void)
503 clock = cm_get_per_vco_clk_hz();
505 /* get the clock prior L4 SP divider (periph_base_clk) */
506 reg = readl(&clock_manager_base->per_pll.perbaseclk);
512 void cm_print_clock_quick_summary(void)
514 printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
515 printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
516 printf("EOSC1 %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
517 printf("EOSC2 %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
518 printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
519 printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
520 printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
521 printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
522 printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
523 printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);