2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/freeze_controller.h>
11 #include <asm/arch/timer.h>
12 #include <asm/errno.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 static const struct socfpga_freeze_controller *freeze_controller_base =
17 (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
20 * Default state from cold reset is FREEZE_ALL; the global
21 * flag is set to TRUE to indicate the IO banks are frozen
23 static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
24 = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
25 FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
28 void sys_mgr_frzctrl_freeze_req(void)
30 u32 ioctrl_reg_offset;
35 /* select software FSM */
36 writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
38 /* Freeze channel 0 to 2 */
39 for (channel_id = 0; channel_id <= 2; channel_id++) {
40 ioctrl_reg_offset = (u32)(
41 &freeze_controller_base->vioctrl + channel_id);
44 * Assert active low enrnsl, plniotri
48 SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
49 | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
50 | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
51 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
54 * Note: Delay for 20ns at min
55 * Assert active low bhniotri signal and de-assert
59 = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
60 | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
61 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
63 /* Set global flag to indicate channel is frozen */
64 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
67 /* Freeze channel 3 */
69 * Assert active low enrnsl, plniotri and
73 = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
74 | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
75 | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
76 clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
79 * assert active low bhniotri & nfrzdrv signals,
80 * de-assert active high csrdone and assert
81 * active high frzreg and nfrzdrv signals
83 reg_value = readl(&freeze_controller_base->hioctrl);
85 = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
86 | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
88 = (reg_value & ~reg_cfg_mask)
89 | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
90 | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
91 writel(reg_value, &freeze_controller_base->hioctrl);
94 * assert active high reinit signal and de-assert
95 * active high pllbiasen signals
97 reg_value = readl(&freeze_controller_base->hioctrl);
100 ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
101 | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
102 writel(reg_value, &freeze_controller_base->hioctrl);
104 /* Set global flag to indicate channel is frozen */
105 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
108 /* Unfreeze/Thaw HPS IOs */
109 void sys_mgr_frzctrl_thaw_req(void)
111 u32 ioctrl_reg_offset;
116 /* select software FSM */
117 writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
119 /* Thaw channel 0 to 2 */
120 for (channel_id = 0; channel_id <= 2; channel_id++) {
122 = (u32)(&freeze_controller_base->vioctrl + channel_id);
125 * Assert active low bhniotri signal and
126 * de-assert active high csrdone
129 = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
130 | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
131 setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
134 * Note: Delay for 20ns at min
135 * de-assert active low plniotri and niotri signals
138 = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
139 | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
140 setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
143 * Note: Delay for 20ns at min
144 * de-assert active low enrnsl signal
146 setbits_le32(ioctrl_reg_offset,
147 SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
149 /* Set global flag to indicate channel is thawed */
150 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
154 /* de-assert active high reinit signal */
155 clrbits_le32(&freeze_controller_base->hioctrl,
156 SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
159 * Note: Delay for 40ns at min
160 * assert active high pllbiasen signals
162 setbits_le32(&freeze_controller_base->hioctrl,
163 SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
166 * Delay 1000 intosc. intosc is based on eosc1
167 * Use worst case which is fatest eosc1=50MHz, delay required
168 * is 1/50MHz * 1000 = 20us
173 * de-assert active low bhniotri signals,
174 * assert active high csrdone and nfrzdrv signal
176 reg_value = readl(&freeze_controller_base->hioctrl);
177 reg_value = (reg_value
178 | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
179 | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
180 & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
181 writel(reg_value, &freeze_controller_base->hioctrl);
185 * Use worst case which is fatest eosc1=50MHz, delay required
186 * is 1/50MHz * 33 = 660ns ~= 1us
190 /* de-assert active low plniotri and niotri signals */
192 = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
193 | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
195 setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
198 * Note: Delay for 40ns at min
199 * de-assert active high frzreg signal
201 clrbits_le32(&freeze_controller_base->hioctrl,
202 SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
205 * Note: Delay for 40ns at min
206 * de-assert active low enrnsl signal
208 setbits_le32(&freeze_controller_base->hioctrl,
209 SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
211 /* Set global flag to indicate channel is thawed */
212 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;