2 * Copyright (C) 2016-2017 Intel Corporation
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef CLOCK_MANAGER_ARRIA10
8 #define CLOCK_MANAGER_ARRIA10
12 struct socfpga_clock_manager_main_pll {
39 struct socfpga_clock_manager_per_pll {
65 struct socfpga_clock_manager_altera {
74 struct socfpga_clock_manager {
85 u32 _pad_0x24_0x40[7];
87 struct socfpga_clock_manager_main_pll main_pll;
89 struct socfpga_clock_manager_per_pll per_pll;
90 struct socfpga_clock_manager_altera altera;
93 void cm_use_intosc(void);
94 unsigned int cm_get_noc_clk_hz(void);
95 unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift);
96 int cm_basic_init(const void *blob);
98 unsigned int cm_get_l4_sp_clk_hz(void);
99 unsigned int cm_get_main_vco_clk_hz(void);
100 unsigned int cm_get_per_vco_clk_hz(void);
101 unsigned long cm_get_mpu_clk_hz(void);
103 unsigned int cm_get_qspi_controller_clk_hz(void);
104 unsigned int cm_get_mmc_controller_clk_hz(void);
105 unsigned int cm_get_spi_controller_clk_hz(void);
107 #endif /* __ASSEMBLER__ */
109 #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
110 #define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
111 #define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
112 CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
115 #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
116 #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
117 #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
118 #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
119 #define CLKMGR_PERPLL_VCO0_RESET 0x00010053
120 #define CLKMGR_PERPLL_VCO1_RESET 0x00010001
121 #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
122 #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
123 #define CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2
124 #define CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0
125 #define CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1
126 #define CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2
127 #define CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3
130 #define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK BIT(6)
131 #define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK BIT(7)
132 #define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK BIT(8)
133 #define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK BIT(9)
134 #define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK BIT(17)
135 #define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
136 #define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK BIT(1)
137 #define CLKMGR_MAINPLL_VCO0_EN_SET_MSK BIT(2)
138 #define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
139 #define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
140 #define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
141 #define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK BIT(1)
142 #define CLKMGR_PERPLL_VCO0_EN_SET_MSK BIT(2)
143 #define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
144 #define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
145 #define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK BIT(0)
146 #define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK BIT(1)
147 #define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK BIT(2)
148 #define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK BIT(3)
149 #define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK BIT(8)
150 #define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK BIT(9)
151 #define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK BIT(10)
152 #define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK BIT(11)
153 #define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK BIT(0)
154 #define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300
155 #define CLKMGR_PERPLL_EN_RESET 0x00000f7f
156 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
157 #define CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003
158 #define CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff
159 #define CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f
160 #define CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff
161 #define CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003
162 #define CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff
163 #define CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f
164 #define CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff
165 #define CLKMGR_MAINPLL_MPUCLK_SRC_MSK 0x00000007
166 #define CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff
167 #define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0
168 #define CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1
169 #define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2
170 #define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3
171 #define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4
172 #define CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003
173 #define CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff
174 #define CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007
175 #define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0
176 #define CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1
177 #define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2
178 #define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3
179 #define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4
181 #define CLKMGR_PERPLLGRP_SRC_MSK 0x00000007
182 #define CLKMGR_PERPLLGRP_SRC_MAIN 0
183 #define CLKMGR_PERPLLGRP_SRC_PERI 1
184 #define CLKMGR_PERPLLGRP_SRC_OSC1 2
185 #define CLKMGR_PERPLLGRP_SRC_INTOSC 3
186 #define CLKMGR_PERPLLGRP_SRC_FPGA 4
188 /* bit shifting macro */
189 #define CLKMGR_MAINPLL_VCO0_PSRC_LSB 8
190 #define CLKMGR_PERPLL_VCO0_PSRC_LSB 8
191 #define CLKMGR_MAINPLL_VCO1_DENOM_LSB 16
192 #define CLKMGR_PERPLL_VCO1_DENOM_LSB 16
193 #define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16
194 #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
195 #define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0
196 #define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8
197 #define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16
198 #define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24
199 #define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26
200 #define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28
201 #define CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16
202 #define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16
203 #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
204 #define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16
205 #define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16
206 #define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
207 #define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
208 #define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
209 #define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
210 #define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
211 #define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
212 #define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
213 #define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
214 #define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
216 /* PLL ramping work around */
217 #define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000
218 #define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000
219 #define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000
220 #define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000
222 #define CLKMGR_STAT_BUSY BIT(0)
224 #endif /* CLOCK_MANAGER_ARRIA10 */