git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/include/mach/nic301.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   4  */
   5
   6 #ifndef _NIC301_REGISTERS_H_
   7 #define _NIC301_REGISTERS_H_
   8
   9 struct nic301_registers {
  10         u32     remap;                          /* 0x0 */
  11         /* Security Register Group */
  12         u32     _pad_0x4_0x8[1];
  13         u32     l4main;
  14         u32     l4sp;
  15         u32     l4mp;                           /* 0x10 */
  16         u32     l4osc1;
  17         u32     l4spim;
  18         u32     stm;
  19         u32     lwhps2fpgaregs;                 /* 0x20 */
  20         u32     _pad_0x24_0x28[1];
  21         u32     usb1;
  22         u32     nanddata;
  23         u32     _pad_0x30_0x80[20];
  24         u32     usb0;                           /* 0x80 */
  25         u32     nandregs;
  26         u32     qspidata;
  27         u32     fpgamgrdata;
  28         u32     hps2fpgaregs;                   /* 0x90 */
  29         u32     acp;
  30         u32     rom;
  31         u32     ocram;
  32         u32     sdrdata;                        /* 0xA0 */
  33         u32     _pad_0xa4_0x1fd0[1995];
  34         /* ID Register Group */
  35         u32     periph_id_4;                    /* 0x1FD0 */
  36         u32     _pad_0x1fd4_0x1fe0[3];
  37         u32     periph_id_0;                    /* 0x1FE0 */
  38         u32     periph_id_1;
  39         u32     periph_id_2;
  40         u32     periph_id_3;
  41         u32     comp_id_0;                      /* 0x1FF0 */
  42         u32     comp_id_1;
  43         u32     comp_id_2;
  44         u32     comp_id_3;
  45         u32     _pad_0x2000_0x2008[2];
  46         /* L4 MAIN */
  47         u32     l4main_fn_mod_bm_iss;
  48         u32     _pad_0x200c_0x3008[1023];
  49         /* L4 SP */
  50         u32     l4sp_fn_mod_bm_iss;
  51         u32     _pad_0x300c_0x4008[1023];
  52         /* L4 MP */
  53         u32     l4mp_fn_mod_bm_iss;
  54         u32     _pad_0x400c_0x5008[1023];
  55         /* L4 OSC1 */
  56         u32     l4osc_fn_mod_bm_iss;
  57         u32     _pad_0x500c_0x6008[1023];
  58         /* L4 SPIM */
  59         u32     l4spim_fn_mod_bm_iss;
  60         u32     _pad_0x600c_0x7008[1023];
  61         /* STM */
  62         u32     stm_fn_mod_bm_iss;
  63         u32     _pad_0x700c_0x7108[63];
  64         u32     stm_fn_mod;
  65         u32     _pad_0x710c_0x8008[959];
  66         /* LWHPS2FPGA */
  67         u32     lwhps2fpga_fn_mod_bm_iss;
  68         u32     _pad_0x800c_0x8108[63];
  69         u32     lwhps2fpga_fn_mod;
  70         u32     _pad_0x810c_0xa008[1983];
  71         /* USB1 */
  72         u32     usb1_fn_mod_bm_iss;
  73         u32     _pad_0xa00c_0xa044[14];
  74         u32     usb1_ahb_cntl;
  75         u32     _pad_0xa048_0xb008[1008];
  76         /* NANDDATA */
  77         u32     nanddata_fn_mod_bm_iss;
  78         u32     _pad_0xb00c_0xb108[63];
  79         u32     nanddata_fn_mod;
  80         u32     _pad_0xb10c_0x20008[21439];
  81         /* USB0 */
  82         u32     usb0_fn_mod_bm_iss;
  83         u32     _pad_0x2000c_0x20044[14];
  84         u32     usb0_ahb_cntl;
  85         u32     _pad_0x20048_0x21008[1008];
  86         /* NANDREGS */
  87         u32     nandregs_fn_mod_bm_iss;
  88         u32     _pad_0x2100c_0x21108[63];
  89         u32     nandregs_fn_mod;
  90         u32     _pad_0x2110c_0x22008[959];
  91         /* QSPIDATA */
  92         u32     qspidata_fn_mod_bm_iss;
  93         u32     _pad_0x2200c_0x22044[14];
  94         u32     qspidata_ahb_cntl;
  95         u32     _pad_0x22048_0x23008[1008];
  96         /* FPGAMGRDATA */
  97         u32     fpgamgrdata_fn_mod_bm_iss;
  98         u32     _pad_0x2300c_0x23040[13];
  99         u32     fpgamgrdata_wr_tidemark;        /* 0x23040 */
 100         u32     _pad_0x23044_0x23108[49];
 101         u32     fn_mod;
 102         u32     _pad_0x2310c_0x24008[959];
 103         /* HPS2FPGA */
 104         u32     hps2fpga_fn_mod_bm_iss;
 105         u32     _pad_0x2400c_0x24040[13];
 106         u32     hps2fpga_wr_tidemark;           /* 0x24040 */
 107         u32     _pad_0x24044_0x24108[49];
 108         u32     hps2fpga_fn_mod;
 109         u32     _pad_0x2410c_0x25008[959];
 110         /* ACP */
 111         u32     acp_fn_mod_bm_iss;
 112         u32     _pad_0x2500c_0x25108[63];
 113         u32     acp_fn_mod;
 114         u32     _pad_0x2510c_0x26008[959];
 115         /* Boot ROM */
 116         u32     bootrom_fn_mod_bm_iss;
 117         u32     _pad_0x2600c_0x26108[63];
 118         u32     bootrom_fn_mod;
 119         u32     _pad_0x2610c_0x27008[959];
 120         /* On-chip RAM */
 121         u32     ocram_fn_mod_bm_iss;
 122         u32     _pad_0x2700c_0x27040[13];
 123         u32     ocram_wr_tidemark;              /* 0x27040 */
 124         u32     _pad_0x27044_0x27108[49];
 125         u32     ocram_fn_mod;
 126         u32     _pad_0x2710c_0x42024[27590];
 127         /* DAP */
 128         u32     dap_fn_mod2;
 129         u32     dap_fn_mod_ahb;
 130         u32     _pad_0x4202c_0x42100[53];
 131         u32     dap_read_qos;                   /* 0x42100 */
 132         u32     dap_write_qos;
 133         u32     dap_fn_mod;
 134         u32     _pad_0x4210c_0x43100[1021];
 135         /* MPU */
 136         u32     mpu_read_qos;                   /* 0x43100 */
 137         u32     mpu_write_qos;
 138         u32     mpu_fn_mod;
 139         u32     _pad_0x4310c_0x44028[967];
 140         /* SDMMC */
 141         u32     sdmmc_fn_mod_ahb;
 142         u32     _pad_0x4402c_0x44100[53];
 143         u32     sdmmc_read_qos;                 /* 0x44100 */
 144         u32     sdmmc_write_qos;
 145         u32     sdmmc_fn_mod;
 146         u32     _pad_0x4410c_0x45100[1021];
 147         /* DMA */
 148         u32     dma_read_qos;                   /* 0x45100 */
 149         u32     dma_write_qos;
 150         u32     dma_fn_mod;
 151         u32     _pad_0x4510c_0x46040[973];
 152         /* FPGA2HPS */
 153         u32     fpga2hps_wr_tidemark;           /* 0x46040 */
 154         u32     _pad_0x46044_0x46100[47];
 155         u32     fpga2hps_read_qos;              /* 0x46100 */
 156         u32     fpga2hps_write_qos;
 157         u32     fpga2hps_fn_mod;
 158         u32     _pad_0x4610c_0x47100[1021];
 159         /* ETR */
 160         u32     etr_read_qos;                   /* 0x47100 */
 161         u32     etr_write_qos;
 162         u32     etr_fn_mod;
 163         u32     _pad_0x4710c_0x48100[1021];
 164         /* EMAC0 */
 165         u32     emac0_read_qos;                 /* 0x48100 */
 166         u32     emac0_write_qos;
 167         u32     emac0_fn_mod;
 168         u32     _pad_0x4810c_0x49100[1021];
 169         /* EMAC1 */
 170         u32     emac1_read_qos;                 /* 0x49100 */
 171         u32     emac1_write_qos;
 172         u32     emac1_fn_mod;
 173         u32     _pad_0x4910c_0x4a028[967];
 174         /* USB0 */
 175         u32     usb0_fn_mod_ahb;
 176         u32     _pad_0x4a02c_0x4a100[53];
 177         u32     usb0_read_qos;                  /* 0x4A100 */
 178         u32     usb0_write_qos;
 179         u32     usb0_fn_mod;
 180         u32     _pad_0x4a10c_0x4b100[1021];
 181         /* NAND */
 182         u32     nand_read_qos;                  /* 0x4B100 */
 183         u32     nand_write_qos;
 184         u32     nand_fn_mod;
 185         u32     _pad_0x4b10c_0x4c028[967];
 186         /* USB1 */
 187         u32     usb1_fn_mod_ahb;
 188         u32     _pad_0x4c02c_0x4c100[53];
 189         u32     usb1_read_qos;                  /* 0x4C100 */
 190         u32     usb1_write_qos;
 191         u32     usb1_fn_mod;
 192 };
 193
 194 #endif  /* _NIC301_REGISTERS_H_ */