2 * Copyright Altera Corporation (C) 2014-2015
4 * SPDX-License-Identifier: GPL-2.0+
11 unsigned long sdram_calculate_size(void);
12 int sdram_mmr_init_full(unsigned int sdr_phy_reg);
13 int sdram_calibration_full(void);
15 const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
17 void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
18 void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
19 const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
20 const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
21 const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void);
23 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
25 struct socfpga_sdr_ctrl {
30 u32 dram_timing4; /* 0x10 */
34 u32 dram_addrw; /* 0x2c */
35 u32 dram_if_width; /* 0x30 */
39 u32 sbe_count; /* 0x40 */
43 u32 drop_addr; /* 0x50 */
47 u32 ctrl_width; /* 0x60 */
51 u32 rfifo_cmap; /* 0x70 */
55 u32 fpgaport_rst; /* 0x80 */
59 u32 prot_rule_addr; /* 0x90 */
64 u32 mp_priority; /* 0xac */
65 u32 mp_weight0; /* 0xb0 */
69 u32 mp_pacing0; /* 0xc0 */
73 u32 mp_threshold0; /* 0xd0 */
77 u32 phy_ctrl0; /* 0x150 */
82 /* SDRAM configuration structure for the SPL. */
83 struct socfpga_sdram_config {
122 struct socfpga_sdram_rw_mgr_config {
124 u8 activate_0_and_1_wait1;
125 u8 activate_0_and_1_wait2;
129 u8 guaranteed_read_cont;
131 u8 guaranteed_write_wait0;
132 u8 guaranteed_write_wait1;
133 u8 guaranteed_write_wait2;
134 u8 guaranteed_write_wait3;
138 u8 init_reset_0_cke_0;
139 u8 init_reset_1_cke_0;
140 u8 lfsr_wr_rd_bank_0;
141 u8 lfsr_wr_rd_bank_0_data;
142 u8 lfsr_wr_rd_bank_0_dqs;
143 u8 lfsr_wr_rd_bank_0_nop;
144 u8 lfsr_wr_rd_bank_0_wait;
145 u8 lfsr_wr_rd_bank_0_wl_1;
146 u8 lfsr_wr_rd_dm_bank_0;
147 u8 lfsr_wr_rd_dm_bank_0_data;
148 u8 lfsr_wr_rd_dm_bank_0_dqs;
149 u8 lfsr_wr_rd_dm_bank_0_nop;
150 u8 lfsr_wr_rd_dm_bank_0_wait;
151 u8 lfsr_wr_rd_dm_bank_0_wl_1;
153 u8 mrs0_dll_reset_mirr;
171 u8 true_mem_data_mask_width;
172 u8 mem_address_mirroring;
173 u8 mem_data_mask_width;
175 u8 mem_dq_per_read_dqs;
176 u8 mem_dq_per_write_dqs;
177 u8 mem_if_read_dqs_width;
178 u8 mem_if_write_dqs_width;
179 u8 mem_number_of_cs_per_dimm;
180 u8 mem_number_of_ranks;
181 u8 mem_virtual_groups_per_read_dqs;
182 u8 mem_virtual_groups_per_write_dqs;
185 struct socfpga_sdram_io_config {
186 u16 delay_per_opa_tap;
187 u8 delay_per_dchain_tap;
188 u8 delay_per_dqs_en_dchain_tap;
190 u8 dqdqs_out_phase_max;
192 u8 dqs_en_delay_offset;
198 u8 io_out1_delay_max;
199 u8 io_out2_delay_max;
200 u8 shift_dqs_en_when_shift_dqs;
203 struct socfpga_sdram_misc_config {
204 u32 reg_file_init_seq_signature;
206 u8 calib_lfifo_offset;
207 u8 calib_vfifo_offset;
208 u8 enable_super_quick_calibration;
209 u8 max_latency_count_width;
210 u8 read_valid_fifo_size;
219 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
220 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
221 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
222 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
223 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
224 #define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
225 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
226 #define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
227 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
228 #define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
229 #define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
230 #define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
231 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
232 #define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
233 #define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
234 #define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
235 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
236 #define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
237 /* Register template: sdr::ctrlgrp::dramtiming1 */
238 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
239 #define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
240 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
241 #define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
242 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
243 #define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
244 #define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
245 #define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
246 #define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
247 #define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
248 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
249 #define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
250 /* Register template: sdr::ctrlgrp::dramtiming2 */
251 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
252 #define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
253 #define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
254 #define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
255 #define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
256 #define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
257 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
258 #define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
259 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
260 #define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
261 /* Register template: sdr::ctrlgrp::dramtiming3 */
262 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
263 #define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
264 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
265 #define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
266 #define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
267 #define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
268 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
269 #define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
270 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
271 #define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
272 /* Register template: sdr::ctrlgrp::dramtiming4 */
273 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
274 #define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
275 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
276 #define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
277 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
278 #define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
279 /* Register template: sdr::ctrlgrp::lowpwrtiming */
280 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
281 #define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
282 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
283 #define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
284 /* Register template: sdr::ctrlgrp::dramaddrw */
285 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
286 #define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
287 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
288 #define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
289 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
290 #define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
291 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
292 #define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
293 /* Register template: sdr::ctrlgrp::dramifwidth */
294 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
295 #define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
296 /* Register template: sdr::ctrlgrp::dramdevwidth */
297 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
298 #define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
299 /* Register template: sdr::ctrlgrp::dramintr */
300 #define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
301 #define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
302 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
303 #define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
304 /* Register template: sdr::ctrlgrp::staticcfg */
305 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
306 #define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
307 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
308 #define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
309 #define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
310 #define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
311 /* Register template: sdr::ctrlgrp::ctrlwidth */
312 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
313 #define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
314 /* Register template: sdr::ctrlgrp::cportwidth */
315 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
316 #define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
317 /* Register template: sdr::ctrlgrp::cportwmap */
318 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
319 #define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
320 /* Register template: sdr::ctrlgrp::cportrmap */
321 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
322 #define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
323 /* Register template: sdr::ctrlgrp::rfifocmap */
324 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
325 #define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
326 /* Register template: sdr::ctrlgrp::wfifocmap */
327 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
328 #define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
329 /* Register template: sdr::ctrlgrp::cportrdwr */
330 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
331 #define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
332 /* Register template: sdr::ctrlgrp::portcfg */
333 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
334 #define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
335 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
336 #define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
337 /* Register template: sdr::ctrlgrp::fifocfg */
338 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
339 #define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
340 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
341 #define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
342 /* Register template: sdr::ctrlgrp::mppriority */
343 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
344 #define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
345 /* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
346 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
347 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
348 /* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
349 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
350 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
351 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
352 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
353 /* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
354 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
355 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
356 /* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
357 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
358 #define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
359 /* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
360 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
361 #define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
362 /* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
363 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
364 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
365 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
366 #define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
367 /* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
368 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
369 #define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
370 /* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
371 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
372 #define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
373 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
375 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
377 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
379 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
381 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
383 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
385 /* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
387 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
389 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
391 /* Register template: sdr::ctrlgrp::remappriority */
392 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
393 #define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
394 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
395 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
396 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
397 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
398 (((x) << 12) & 0xfffff000)
399 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
400 (((x) << 10) & 0x00000c00)
401 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
402 (((x) << 6) & 0x000000c0)
403 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
404 (((x) << 8) & 0x00000100)
405 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
406 (((x) << 9) & 0x00000200)
407 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
408 (((x) << 4) & 0x00000030)
409 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
410 (((x) << 2) & 0x0000000c)
411 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
412 (((x) << 0) & 0x00000003)
413 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
414 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
415 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
416 (((x) << 12) & 0xfffff000)
417 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
418 (((x) << 0) & 0x00000fff)
419 /* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
420 #define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
421 (((x) << 0) & 0x00000fff)
422 /* Register template: sdr::ctrlgrp::dramodt */
423 #define SDR_CTRLGRP_DRAMODT_READ_LSB 4
424 #define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
425 #define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
426 #define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
427 /* Field instance: sdr::ctrlgrp::dramsts */
428 #define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
429 #define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
431 /* SDRAM width macro for configuration with ECC */
432 #define SDRAM_WIDTH_32BIT_WITH_ECC 40
433 #define SDRAM_WIDTH_16BIT_WITH_ECC 24
436 #endif /* _SDRAM_H_ */