git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/include/mach/system_manager.h

   1 /*
   2  * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _SYSTEM_MANAGER_H_
   8 #define _SYSTEM_MANAGER_H_
   9
  10 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
  11 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO     BIT(1)
  12 #define SYSMGR_ECC_OCRAM_EN     BIT(0)
  13 #define SYSMGR_ECC_OCRAM_SERR   BIT(3)
  14 #define SYSMGR_ECC_OCRAM_DERR   BIT(4)
  15 #define SYSMGR_FPGAINTF_USEFPGA 0x1
  16 #define SYSMGR_FPGAINTF_SPIM0   BIT(0)
  17 #define SYSMGR_FPGAINTF_SPIM1   BIT(1)
  18 #define SYSMGR_FPGAINTF_EMAC0   BIT(2)
  19 #define SYSMGR_FPGAINTF_EMAC1   BIT(3)
  20 #define SYSMGR_FPGAINTF_NAND    BIT(4)
  21 #define SYSMGR_FPGAINTF_SDMMC   BIT(5)
  22
  23 #define SYSMGR_SDMMC_DRVSEL_SHIFT       0
  24
  25 /* EMAC Group Bit definitions */
  26 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII        0x0
  27 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII           0x1
  28 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII            0x2
  29
  30 #define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB                 0
  31 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB                 2
  32 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK                 0x3
  33
  34 /* For dedicated IO configuration */
  35 /* Voltage select enums */
  36 #define VOLTAGE_SEL_3V          0x0
  37 #define VOLTAGE_SEL_1P8V        0x1
  38 #define VOLTAGE_SEL_2P5V        0x2
  39
  40 /* Input buffer enable */
  41 #define INPUT_BUF_DISABLE       0
  42 #define INPUT_BUF_1P8V          1
  43 #define INPUT_BUF_2P5V3V        2
  44
  45 /* Weak pull up enable */
  46 #define WK_PU_DISABLE           0
  47 #define WK_PU_ENABLE            1
  48
  49 /* Pull up slew rate control */
  50 #define PU_SLW_RT_SLOW          0
  51 #define PU_SLW_RT_FAST          1
  52 #define PU_SLW_RT_DEFAULT       PU_SLW_RT_SLOW
  53
  54 /* Pull down slew rate control */
  55 #define PD_SLW_RT_SLOW          0
  56 #define PD_SLW_RT_FAST          1
  57 #define PD_SLW_RT_DEFAULT       PD_SLW_RT_SLOW
  58
  59 /* Drive strength control */
  60 #define PU_DRV_STRG_DEFAULT     0x10
  61 #define PD_DRV_STRG_DEFAULT     0x10
  62
  63 /* bit position */
  64 #define PD_DRV_STRG_LSB         0
  65 #define PD_SLW_RT_LSB           5
  66 #define PU_DRV_STRG_LSB         8
  67 #define PU_SLW_RT_LSB           13
  68 #define WK_PU_LSB               16
  69 #define INPUT_BUF_LSB           17
  70 #define BIAS_TRIM_LSB           19
  71 #define VOLTAGE_SEL_LSB         0
  72
  73 #define ALT_SYSMGR_NOC_H2F_SET_MSK      BIT(0)
  74 #define ALT_SYSMGR_NOC_LWH2F_SET_MSK    BIT(4)
  75 #define ALT_SYSMGR_NOC_F2H_SET_MSK      BIT(8)
  76 #define ALT_SYSMGR_NOC_F2SDR0_SET_MSK   BIT(16)
  77 #define ALT_SYSMGR_NOC_F2SDR1_SET_MSK   BIT(20)
  78 #define ALT_SYSMGR_NOC_F2SDR2_SET_MSK   BIT(24)
  79 #define ALT_SYSMGR_NOC_TMO_EN_SET_MSK   BIT(0)
  80
  81 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK       BIT(1)
  82 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK       BIT(1)
  83
  84 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  85 #include <asm/arch/system_manager_gen5.h>
  86 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  87 #include <asm/arch/system_manager_arria10.h>
  88 #endif
  89
  90 #define SYSMGR_GET_BOOTINFO_BSEL(bsel)          \
  91                 (((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
  92
  93 #endif /* _SYSTEM_MANAGER_H_ */