git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/include/mach/system_manager_arria10.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
   4  */
   5
   6 #ifndef _SYSTEM_MANAGER_ARRIA10_H_
   7 #define _SYSTEM_MANAGER_ARRIA10_H_
   8
   9 struct socfpga_system_manager {
  10         u32  siliconid1;
  11         u32  siliconid2;
  12         u32  wddbg;
  13         u32  bootinfo;
  14         u32  mpu_ctrl_l2_ecc;
  15         u32  _pad_0x14_0x1f[3];
  16         u32  dma;
  17         u32  dma_periph;
  18         u32  sdmmcgrp_ctrl;
  19         u32  sdmmc_l3master;
  20         u32  nand_bootstrap;
  21         u32  nand_l3master;
  22         u32  usb0_l3master;
  23         u32  usb1_l3master;
  24         u32  emac_global;
  25         u32  emac[3];
  26         u32  _pad_0x50_0x5f[4];
  27         u32  fpgaintf_en_global;
  28         u32  fpgaintf_en_0;
  29         u32  fpgaintf_en_1;
  30         u32  fpgaintf_en_2;
  31         u32  fpgaintf_en_3;
  32         u32  _pad_0x74_0x7f[3];
  33         u32  noc_addr_remap_value;
  34         u32  noc_addr_remap_set;
  35         u32  noc_addr_remap_clear;
  36         u32  _pad_0x8c_0x8f;
  37         u32  ecc_intmask_value;
  38         u32  ecc_intmask_set;
  39         u32  ecc_intmask_clr;
  40         u32  ecc_intstatus_serr;
  41         u32  ecc_intstatus_derr;
  42         u32  mpu_status_l2_ecc;
  43         u32  mpu_clear_l2_ecc;
  44         u32  mpu_status_l1_parity;
  45         u32  mpu_clear_l1_parity;
  46         u32  mpu_set_l1_parity;
  47         u32  _pad_0xb8_0xbf[2];
  48         u32  noc_timeout;
  49         u32  noc_idlereq_set;
  50         u32  noc_idlereq_clr;
  51         u32  noc_idlereq_value;
  52         u32  noc_idleack;
  53         u32  noc_idlestatus;
  54         u32  fpga2soc_ctrl;
  55         u32  _pad_0xdc_0xff[9];
  56         u32  tsmc_tsel_0;
  57         u32  tsmc_tsel_1;
  58         u32  tsmc_tsel_2;
  59         u32  tsmc_tsel_3;
  60         u32  _pad_0x110_0x200[60];
  61         u32  romhw_ctrl;
  62         u32  romcode_ctrl;
  63         u32  romcode_cpu1startaddr;
  64         u32  romcode_initswstate;
  65         u32  romcode_initswlastld;
  66         u32  _pad_0x214_0x217;
  67         u32  warmram_enable;
  68         u32  warmram_datastart;
  69         u32  warmram_length;
  70         u32  warmram_execution;
  71         u32  warmram_crc;
  72         u32  _pad_0x22c_0x22f;
  73         u32  isw_handoff[8];
  74         u32  romcode_bootromswstate[8];
  75 };
  76
  77 #define SYSMGR_SDMMC_SMPLSEL_SHIFT      4
  78 #define SYSMGR_BOOTINFO_BSEL_SHIFT      12
  79
  80 #endif /* _SYSTEM_MANAGER_ARRIA10_H_ */