2 * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _SYSTEM_MANAGER_ARRIA10_H_
8 #define _SYSTEM_MANAGER_ARRIA10_H_
10 struct socfpga_system_manager {
16 u32 _pad_0x14_0x1f[3];
27 u32 _pad_0x50_0x5f[4];
28 u32 fpgaintf_en_global;
33 u32 _pad_0x74_0x7f[3];
34 u32 noc_addr_remap_value;
35 u32 noc_addr_remap_set;
36 u32 noc_addr_remap_clear;
38 u32 ecc_intmask_value;
41 u32 ecc_intstatus_serr;
42 u32 ecc_intstatus_derr;
43 u32 mpu_status_l2_ecc;
45 u32 mpu_status_l1_parity;
46 u32 mpu_clear_l1_parity;
47 u32 mpu_set_l1_parity;
48 u32 _pad_0xb8_0xbf[2];
52 u32 noc_idlereq_value;
56 u32 _pad_0xdc_0xff[9];
61 u32 _pad_0x110_0x200[60];
64 u32 romcode_cpu1startaddr;
65 u32 romcode_initswstate;
66 u32 romcode_initswlastld;
69 u32 warmram_datastart;
71 u32 warmram_execution;
75 u32 romcode_bootromswstate[8];
78 #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
79 #define SYSMGR_BOOTINFO_BSEL_SHIFT 12
81 #endif /* _SYSTEM_MANAGER_ARRIA10_H_ */