2 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/misc.h>
17 #include <asm/arch/reset_manager.h>
18 #include <asm/arch/scan_manager.h>
19 #include <asm/arch/system_manager.h>
20 #include <asm/arch/nic301.h>
21 #include <asm/arch/scu.h>
22 #include <asm/pl310.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 static const struct pl310_regs *const pl310 =
27 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
29 struct bsel bsel_str[] = {
30 { "rsvd", "Reserved", },
31 { "fpga", "FPGA (HPS2FPGA Bridge)", },
32 { "nand", "NAND Flash (1.8V)", },
33 { "nand", "NAND Flash (3.0V)", },
34 { "sd", "SD/MMC External Transceiver (1.8V)", },
35 { "sd", "SD/MMC Internal Transceiver (3.0V)", },
36 { "qspi", "QSPI Flash (1.8V)", },
37 { "qspi", "QSPI Flash (3.0V)", },
42 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
46 void enable_caches(void)
48 #ifndef CONFIG_SYS_ICACHE_OFF
51 #ifndef CONFIG_SYS_DCACHE_OFF
56 void v7_outer_cache_enable(void)
58 /* Disable the L2 cache */
59 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
61 /* enable BRESP, instruction and data prefetch, full line of zeroes */
62 setbits_le32(&pl310->pl310_aux_ctrl,
63 L310_AUX_CTRL_DATA_PREFETCH_MASK |
64 L310_AUX_CTRL_INST_PREFETCH_MASK |
65 L310_SHARED_ATT_OVERRIDE_ENABLE);
67 /* Enable the L2 cache */
68 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
71 void v7_outer_cache_disable(void)
73 /* Disable the L2 cache */
74 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
77 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
78 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
79 int overwrite_console(void)
87 * FPGA programming support for SoC FPGA Cyclone V
89 static Altera_desc altera_fpga[] = {
94 fast_passive_parallel,
95 /* No limitation as additional data will be ignored */
97 /* No device function table */
99 /* Base interface address specified in driver */
101 /* No cookie implementation */
106 /* add device descriptor to FPGA device table */
107 void socfpga_fpga_add(void)
111 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
112 fpga_add(fpga_altera, &altera_fpga[i]);
116 int arch_cpu_init(void)
118 #ifdef CONFIG_HW_WATCHDOG
120 * In case the watchdog is enabled, make sure to (re-)configure it
121 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
122 * timeout value is still active which might too short for Linux
128 * If the HW watchdog is NOT enabled, make sure it is not running,
129 * for example because it was enabled in the preloader. This might
130 * trigger a watchdog-triggered reboot of Linux kernel later.
131 * Toggle watchdog reset, so watchdog in not running state.
133 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
134 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);