2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/reset_manager.h>
17 #include <asm/arch/scan_manager.h>
18 #include <asm/arch/system_manager.h>
19 #include <asm/arch/dwmmc.h>
20 #include <asm/arch/nic301.h>
21 #include <asm/arch/scu.h>
22 #include <asm/pl310.h>
24 #include <dt-bindings/reset/altr,rst-mgr.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 static struct pl310_regs *const pl310 =
29 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
30 static struct socfpga_system_manager *sysmgr_regs =
31 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
32 static struct socfpga_reset_manager *reset_manager_base =
33 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
34 static struct nic301_registers *nic301_regs =
35 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
36 static struct scu_registers *scu_regs =
37 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
41 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
45 void enable_caches(void)
47 #ifndef CONFIG_SYS_ICACHE_OFF
50 #ifndef CONFIG_SYS_DCACHE_OFF
55 void v7_outer_cache_enable(void)
57 /* disable the L2 cache */
58 writel(0, &pl310->pl310_ctrl);
60 /* enable BRESP, instruction and data prefetch, full line of zeroes */
61 setbits_le32(&pl310->pl310_aux_ctrl,
62 L310_AUX_CTRL_DATA_PREFETCH_MASK |
63 L310_AUX_CTRL_INST_PREFETCH_MASK |
64 L310_SHARED_ATT_OVERRIDE_ENABLE);
68 * DesignWare Ethernet initialization
70 #ifdef CONFIG_ETH_DESIGNWARE
71 static void dwmac_deassert_reset(const unsigned int of_reset_id)
75 if (of_reset_id == EMAC0_RESET) {
76 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
77 reset = SOCFPGA_RESET(EMAC0);
78 } else if (of_reset_id == EMAC1_RESET) {
79 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
80 reset = SOCFPGA_RESET(EMAC1);
82 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
86 /* Clearing emac0 PHY interface select to 0 */
87 clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
88 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
90 /* configure to PHY interface select choosed */
91 setbits_le32(&sysmgr_regs->emacgrp_ctrl,
92 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
94 /* Release the EMAC controller from reset */
95 socfpga_per_reset(reset, 0);
98 int cpu_eth_init(bd_t *bis)
100 const void *fdt = gd->fdt_blob;
101 struct fdtdec_phandle_args args;
102 int nodes[2]; /* Max. two GMACs */
106 /* Put both GMACs into RESET state. */
107 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
108 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
110 count = fdtdec_find_aliases_for_id(fdt, "ethernet",
111 COMPAT_ALTERA_SOCFPGA_DWMAC,
112 nodes, ARRAY_SIZE(nodes));
113 for (i = 0; i < count; i++) {
118 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
119 "#reset-cells", 1, 0,
121 if (ret || (args.args_count != 1)) {
122 debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
126 dwmac_deassert_reset(args.args[0]);
135 * Initializes MMC controllers.
136 * to override, implement board_mmc_init()
138 int cpu_mmc_init(bd_t *bis)
140 return socfpga_dwmmc_init(gd->fdt_blob);
148 { "rsvd", "Reserved", },
149 { "fpga", "FPGA (HPS2FPGA Bridge)", },
150 { "nand", "NAND Flash (1.8V)", },
151 { "nand", "NAND Flash (3.0V)", },
152 { "sd", "SD/MMC External Transceiver (1.8V)", },
153 { "sd", "SD/MMC Internal Transceiver (3.0V)", },
154 { "qspi", "QSPI Flash (1.8V)", },
155 { "qspi", "QSPI Flash (3.0V)", },
158 static const struct {
162 } const socfpga_fpga_model[] = {
164 { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
165 { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
166 { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
167 { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
168 { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
169 /* Cyclone V GX/GT */
170 { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
171 { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
172 { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
173 { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
174 { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
175 /* Cyclone V SE/SX/ST */
176 { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
177 { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
178 { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
179 { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
181 { 0x2d03, "Arria V, D5", "av_d5" },
184 static int socfpga_fpga_id(const bool print_id)
186 const u32 altera_mi = 0x6e;
187 const u32 id = scan_mgr_get_fpga_id();
189 const u32 lsb = id & 0x00000001;
190 const u32 mi = (id >> 1) & 0x000007ff;
191 const u32 pn = (id >> 12) & 0x0000ffff;
192 const u32 version = (id >> 28) & 0x0000000f;
195 if ((mi != altera_mi) || (lsb != 1)) {
196 printf("FPGA: Not Altera chip ID\n");
200 for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
201 if (pn == socfpga_fpga_model[i].pn)
204 if (i == ARRAY_SIZE(socfpga_fpga_model)) {
205 printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id);
210 printf("FPGA: Altera %s, version 0x%01x\n",
211 socfpga_fpga_model[i].name, version);
216 * Print CPU information
218 #if defined(CONFIG_DISPLAY_CPUINFO)
219 int print_cpuinfo(void)
221 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
222 puts("CPU: Altera SoCFPGA Platform\n");
224 printf("BOOT: %s\n", bsel_str[bsel].name);
229 #ifdef CONFIG_ARCH_MISC_INIT
230 int arch_misc_init(void)
232 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
233 const int fpga_id = socfpga_fpga_id(0);
234 setenv("bootmode", bsel_str[bsel].mode);
236 setenv("fpgatype", socfpga_fpga_model[fpga_id].var);
241 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
242 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
243 int overwrite_console(void)
251 * FPGA programming support for SoC FPGA Cyclone V
253 static Altera_desc altera_fpga[] = {
258 fast_passive_parallel,
259 /* No limitation as additional data will be ignored */
261 /* No device function table */
263 /* Base interface address specified in driver */
265 /* No cookie implementation */
270 /* add device descriptor to FPGA device table */
271 static void socfpga_fpga_add(void)
275 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
276 fpga_add(fpga_altera, &altera_fpga[i]);
279 static inline void socfpga_fpga_add(void) {}
282 int arch_cpu_init(void)
284 #ifdef CONFIG_HW_WATCHDOG
286 * In case the watchdog is enabled, make sure to (re-)configure it
287 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
288 * timeout value is still active which might too short for Linux
294 * If the HW watchdog is NOT enabled, make sure it is not running,
295 * for example because it was enabled in the preloader. This might
296 * trigger a watchdog-triggered reboot of Linux kernel later.
297 * Toggle watchdog reset, so watchdog in not running state.
299 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
300 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
307 * Convert all NIC-301 AMBA slaves from secure to non-secure
309 static void socfpga_nic301_slave_ns(void)
311 writel(0x1, &nic301_regs->lwhps2fpgaregs);
312 writel(0x1, &nic301_regs->hps2fpgaregs);
313 writel(0x1, &nic301_regs->acp);
314 writel(0x1, &nic301_regs->rom);
315 writel(0x1, &nic301_regs->ocram);
316 writel(0x1, &nic301_regs->sdrdata);
319 static uint32_t iswgrp_handoff[8];
321 int arch_early_init_r(void)
326 * Write magic value into magic register to unlock support for
327 * issuing warm reset. The ancient kernel code expects this
328 * value to be written into the register by the bootloader, so
329 * to support that old code, we write it here instead of in the
330 * reset_cpu() function just before reseting the CPU.
332 writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
334 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
335 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
337 socfpga_bridges_reset(1);
338 socfpga_nic301_slave_ns();
341 * Private components security:
342 * U-Boot : configure private timer, global timer and cpu component
343 * access as non secure for kernel stage (as required by Linux)
345 setbits_le32(&scu_regs->sacr, 0xfff);
347 /* Configure the L2 controller to make SDRAM start at 0 */
348 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
349 writel(0x2, &nic301_regs->remap);
351 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
352 writel(0x1, &pl310->pl310_addr_filter_start);
355 /* Add device descriptor to FPGA device table */
358 #ifdef CONFIG_DESIGNWARE_SPI
359 /* Get Designware SPI controller out of reset */
360 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
361 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
367 static void socfpga_sdram_apply_static_cfg(void)
369 const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
370 const uint32_t applymask = 0x8;
371 uint32_t val = readl(staticcfg) | applymask;
374 * SDRAM staticcfg register specific:
375 * When applying the register setting, the CPU must not access
376 * SDRAM. Luckily for us, we can abuse i-cache here to help us
377 * circumvent the SDRAM access issue. The idea is to make sure
378 * that the code is in one full i-cache line by branching past
379 * it and back. Once it is in the i-cache, we execute the core
380 * of the code and apply the register settings.
382 * The code below uses 7 instructions, while the Cortex-A9 has
383 * 32-byte cachelines, thus the limit is 8 instructions total.
394 : : "r"(val), "r"(staticcfg) : "memory", "cc");
397 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
400 return CMD_RET_USAGE;
405 case 'e': /* Enable */
406 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
407 socfpga_sdram_apply_static_cfg();
408 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
409 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
410 writel(iswgrp_handoff[1], &nic301_regs->remap);
412 case 'd': /* Disable */
413 writel(0, &sysmgr_regs->fpgaintfgrp_module);
414 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
415 socfpga_sdram_apply_static_cfg();
416 writel(0, &reset_manager_base->brg_mod_reset);
417 writel(1, &nic301_regs->remap);
420 return CMD_RET_USAGE;
427 bridge, 2, 1, do_bridge,
428 "SoCFPGA HPS FPGA bridge control",
429 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
430 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"