git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/misc.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <altera.h>
  10 #include <miiphy.h>
  11 #include <netdev.h>
  12 #include <watchdog.h>
  13 #include <asm/arch/reset_manager.h>
  14 #include <asm/arch/system_manager.h>
  15 #include <asm/arch/dwmmc.h>
  16 #include <asm/arch/nic301.h>
  17 #include <asm/arch/scu.h>
  18 #include <asm/pl310.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 static struct pl310_regs *const pl310 =
  23         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  24 static struct socfpga_system_manager *sysmgr_regs =
  25         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  26 static struct socfpga_reset_manager *reset_manager_base =
  27         (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
  28 static struct nic301_registers *nic301_regs =
  29         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  30 static struct scu_registers *scu_regs =
  31         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  32
  33 int dram_init(void)
  34 {
  35         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  36         return 0;
  37 }
  38
  39 void enable_caches(void)
  40 {
  41 #ifndef CONFIG_SYS_ICACHE_OFF
  42         icache_enable();
  43 #endif
  44 #ifndef CONFIG_SYS_DCACHE_OFF
  45         dcache_enable();
  46 #endif
  47 }
  48
  49 /*
  50  * DesignWare Ethernet initialization
  51  */
  52 #ifdef CONFIG_ETH_DESIGNWARE
  53 int cpu_eth_init(bd_t *bis)
  54 {
  55 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
  56         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  57         const u32 reset = SOCFPGA_RESET(EMAC0);
  58 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
  59         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  60         const u32 reset = SOCFPGA_RESET(EMAC1);
  61 #else
  62 #error "Incorrect CONFIG_EMAC_BASE value!"
  63 #endif
  64
  65         /* Initialize EMAC. This needs to be done at least once per boot. */
  66
  67         /*
  68          * Putting the EMAC controller to reset when configuring the PHY
  69          * interface select at System Manager
  70          */
  71         socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
  72         socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
  73
  74         /* Clearing emac0 PHY interface select to 0 */
  75         clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
  76                      SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
  77
  78         /* configure to PHY interface select choosed */
  79         setbits_le32(&sysmgr_regs->emacgrp_ctrl,
  80                      SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
  81
  82         /* Release the EMAC controller from reset */
  83         socfpga_per_reset(reset, 0);
  84
  85         /* initialize and register the emac */
  86         return designware_initialize(CONFIG_EMAC_BASE,
  87                                      CONFIG_PHY_INTERFACE_MODE);
  88 }
  89 #endif
  90
  91 #ifdef CONFIG_DWMMC
  92 /*
  93  * Initializes MMC controllers.
  94  * to override, implement board_mmc_init()
  95  */
  96 int cpu_mmc_init(bd_t *bis)
  97 {
  98         return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
  99                                   CONFIG_HPS_SDMMC_BUSWIDTH, 0);
 100 }
 101 #endif
 102
 103 struct {
 104         const char      *mode;
 105         const char      *name;
 106 } bsel_str[] = {
 107         { "rsvd", "Reserved", },
 108         { "fpga", "FPGA (HPS2FPGA Bridge)", },
 109         { "nand", "NAND Flash (1.8V)", },
 110         { "nand", "NAND Flash (3.0V)", },
 111         { "sd", "SD/MMC External Transceiver (1.8V)", },
 112         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
 113         { "qspi", "QSPI Flash (1.8V)", },
 114         { "qspi", "QSPI Flash (3.0V)", },
 115 };
 116
 117 /*
 118  * Print CPU information
 119  */
 120 #if defined(CONFIG_DISPLAY_CPUINFO)
 121 int print_cpuinfo(void)
 122 {
 123         const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 124         puts("CPU:   Altera SoCFPGA Platform\n");
 125         printf("BOOT:  %s\n", bsel_str[bsel].name);
 126         return 0;
 127 }
 128 #endif
 129
 130 #ifdef CONFIG_ARCH_MISC_INIT
 131 int arch_misc_init(void)
 132 {
 133         const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 134         setenv("bootmode", bsel_str[bsel].mode);
 135         return 0;
 136 }
 137 #endif
 138
 139 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 140 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 141 int overwrite_console(void)
 142 {
 143         return 0;
 144 }
 145 #endif
 146
 147 #ifdef CONFIG_FPGA
 148 /*
 149  * FPGA programming support for SoC FPGA Cyclone V
 150  */
 151 static Altera_desc altera_fpga[] = {
 152         {
 153                 /* Family */
 154                 Altera_SoCFPGA,
 155                 /* Interface type */
 156                 fast_passive_parallel,
 157                 /* No limitation as additional data will be ignored */
 158                 -1,
 159                 /* No device function table */
 160                 NULL,
 161                 /* Base interface address specified in driver */
 162                 NULL,
 163                 /* No cookie implementation */
 164                 0
 165         },
 166 };
 167
 168 /* add device descriptor to FPGA device table */
 169 static void socfpga_fpga_add(void)
 170 {
 171         int i;
 172         fpga_init();
 173         for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
 174                 fpga_add(fpga_altera, &altera_fpga[i]);
 175 }
 176 #else
 177 static inline void socfpga_fpga_add(void) {}
 178 #endif
 179
 180 int arch_cpu_init(void)
 181 {
 182 #ifdef CONFIG_HW_WATCHDOG
 183         /*
 184          * In case the watchdog is enabled, make sure to (re-)configure it
 185          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 186          * timeout value is still active which might too short for Linux
 187          * booting.
 188          */
 189         hw_watchdog_init();
 190 #else
 191         /*
 192          * If the HW watchdog is NOT enabled, make sure it is not running,
 193          * for example because it was enabled in the preloader. This might
 194          * trigger a watchdog-triggered reboot of Linux kernel later.
 195          * Toggle watchdog reset, so watchdog in not running state.
 196          */
 197         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 198         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 199 #endif
 200
 201         return 0;
 202 }
 203
 204 /*
 205  * Convert all NIC-301 AMBA slaves from secure to non-secure
 206  */
 207 static void socfpga_nic301_slave_ns(void)
 208 {
 209         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 210         writel(0x1, &nic301_regs->hps2fpgaregs);
 211         writel(0x1, &nic301_regs->acp);
 212         writel(0x1, &nic301_regs->rom);
 213         writel(0x1, &nic301_regs->ocram);
 214         writel(0x1, &nic301_regs->sdrdata);
 215 }
 216
 217 static uint32_t iswgrp_handoff[8];
 218
 219 int arch_early_init_r(void)
 220 {
 221         int i;
 222
 223         /*
 224          * Write magic value into magic register to unlock support for
 225          * issuing warm reset. The ancient kernel code expects this
 226          * value to be written into the register by the bootloader, so
 227          * to support that old code, we write it here instead of in the
 228          * reset_cpu() function just before reseting the CPU.
 229          */
 230         writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
 231
 232         for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
 233                 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
 234
 235         socfpga_bridges_reset(1);
 236         socfpga_nic301_slave_ns();
 237
 238         /*
 239          * Private components security:
 240          * U-Boot : configure private timer, global timer and cpu component
 241          * access as non secure for kernel stage (as required by Linux)
 242          */
 243         setbits_le32(&scu_regs->sacr, 0xfff);
 244
 245         /* Configure the L2 controller to make SDRAM start at 0 */
 246 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 247         writel(0x2, &nic301_regs->remap);
 248 #else
 249         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
 250         writel(0x1, &pl310->pl310_addr_filter_start);
 251 #endif
 252
 253         /* Add device descriptor to FPGA device table */
 254         socfpga_fpga_add();
 255
 256 #ifdef CONFIG_DESIGNWARE_SPI
 257         /* Get Designware SPI controller out of reset */
 258         socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
 259         socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
 260 #endif
 261
 262         return 0;
 263 }
 264
 265 static void socfpga_sdram_apply_static_cfg(void)
 266 {
 267         const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
 268         const uint32_t applymask = 0x8;
 269         uint32_t val = readl(staticcfg) | applymask;
 270
 271         /*
 272          * SDRAM staticcfg register specific:
 273          * When applying the register setting, the CPU must not access
 274          * SDRAM. Luckily for us, we can abuse i-cache here to help us
 275          * circumvent the SDRAM access issue. The idea is to make sure
 276          * that the code is in one full i-cache line by branching past
 277          * it and back. Once it is in the i-cache, we execute the core
 278          * of the code and apply the register settings.
 279          *
 280          * The code below uses 7 instructions, while the Cortex-A9 has
 281          * 32-byte cachelines, thus the limit is 8 instructions total.
 282          */
 283         asm volatile(
 284                 ".align 5                       \n"
 285                 "       b       2f              \n"
 286                 "1:     str     %0,     [%1]    \n"
 287                 "       dsb                     \n"
 288                 "       isb                     \n"
 289                 "       b       3f              \n"
 290                 "2:     b       1b              \n"
 291                 "3:     nop                     \n"
 292         : : "r"(val), "r"(staticcfg) : "memory", "cc");
 293 }
 294
 295 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 296 {
 297         if (argc != 2)
 298                 return CMD_RET_USAGE;
 299
 300         argv++;
 301
 302         switch (*argv[0]) {
 303         case 'e':       /* Enable */
 304                 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
 305                 socfpga_sdram_apply_static_cfg();
 306                 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
 307                 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
 308                 writel(iswgrp_handoff[1], &nic301_regs->remap);
 309                 break;
 310         case 'd':       /* Disable */
 311                 writel(0, &sysmgr_regs->fpgaintfgrp_module);
 312                 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
 313                 socfpga_sdram_apply_static_cfg();
 314                 writel(0, &reset_manager_base->brg_mod_reset);
 315                 writel(1, &nic301_regs->remap);
 316                 break;
 317         default:
 318                 return CMD_RET_USAGE;
 319         }
 320
 321         return 0;
 322 }
 323
 324 U_BOOT_CMD(
 325         bridge, 2, 1, do_bridge,
 326         "SoCFPGA HPS FPGA bridge control",
 327         "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 328         "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 329         ""
 330 );