git.sur5r.net Git - u-boot/blob - arch/arm/mach-socfpga/misc_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <linux/libfdt.h>
  11 #include <altera.h>
  12 #include <miiphy.h>
  13 #include <netdev.h>
  14 #include <watchdog.h>
  15 #include <asm/arch/misc.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <asm/arch/scan_manager.h>
  18 #include <asm/arch/sdram.h>
  19 #include <asm/arch/system_manager.h>
  20 #include <asm/arch/nic301.h>
  21 #include <asm/arch/scu.h>
  22 #include <asm/pl310.h>
  23
  24 #include <dt-bindings/reset/altr,rst-mgr.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static struct pl310_regs *const pl310 =
  29         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  30 static struct socfpga_system_manager *sysmgr_regs =
  31         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  32 static struct nic301_registers *nic301_regs =
  33         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  34 static struct scu_registers *scu_regs =
  35         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  36
  37 /*
  38  * DesignWare Ethernet initialization
  39  */
  40 #ifdef CONFIG_ETH_DESIGNWARE
  41 void dwmac_deassert_reset(const unsigned int of_reset_id,
  42                                  const u32 phymode)
  43 {
  44         u32 physhift, reset;
  45
  46         if (of_reset_id == EMAC0_RESET) {
  47                 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  48                 reset = SOCFPGA_RESET(EMAC0);
  49         } else if (of_reset_id == EMAC1_RESET) {
  50                 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  51                 reset = SOCFPGA_RESET(EMAC1);
  52         } else {
  53                 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
  54                 return;
  55         }
  56
  57         /* configure to PHY interface select choosed */
  58         clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
  59                         SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
  60                         phymode << physhift);
  61
  62         /* Release the EMAC controller from reset */
  63         socfpga_per_reset(reset, 0);
  64 }
  65
  66 static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
  67 {
  68         if (!phymode)
  69                 return -EINVAL;
  70
  71         if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
  72                 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
  73                 return 0;
  74         }
  75
  76         if (!strcmp(phymode, "rgmii")) {
  77                 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
  78                 return 0;
  79         }
  80
  81         if (!strcmp(phymode, "rmii")) {
  82                 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
  83                 return 0;
  84         }
  85
  86         return -EINVAL;
  87 }
  88
  89 static int socfpga_eth_reset(void)
  90 {
  91         const void *fdt = gd->fdt_blob;
  92         struct fdtdec_phandle_args args;
  93         const char *phy_mode;
  94         u32 phy_modereg;
  95         int nodes[2];   /* Max. two GMACs */
  96         int ret, count;
  97         int i, node;
  98
  99         /* Put both GMACs into RESET state. */
 100         socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
 101         socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
 102
 103         count = fdtdec_find_aliases_for_id(fdt, "ethernet",
 104                                            COMPAT_ALTERA_SOCFPGA_DWMAC,
 105                                            nodes, ARRAY_SIZE(nodes));
 106         for (i = 0; i < count; i++) {
 107                 node = nodes[i];
 108                 if (node <= 0)
 109                         continue;
 110
 111                 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
 112                                                      "#reset-cells", 1, 0,
 113                                                      &args);
 114                 if (ret || (args.args_count != 1)) {
 115                         debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
 116                         continue;
 117                 }
 118
 119                 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
 120                 ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
 121                 if (ret) {
 122                         debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
 123                         continue;
 124                 }
 125
 126                 dwmac_deassert_reset(args.args[0], phy_modereg);
 127         }
 128
 129         return 0;
 130 }
 131 #else
 132 static int socfpga_eth_reset(void)
 133 {
 134         return 0;
 135 };
 136 #endif
 137
 138 static const struct {
 139         const u16       pn;
 140         const char      *name;
 141         const char      *var;
 142 } socfpga_fpga_model[] = {
 143         /* Cyclone V E */
 144         { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
 145         { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
 146         { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
 147         { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
 148         { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
 149         /* Cyclone V GX/GT */
 150         { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
 151         { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
 152         { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
 153         { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
 154         { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
 155         /* Cyclone V SE/SX/ST */
 156         { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
 157         { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
 158         { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
 159         { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
 160         /* Arria V */
 161         { 0x2d03, "Arria V, D5", "av_d5" },
 162 };
 163
 164 static int socfpga_fpga_id(const bool print_id)
 165 {
 166         const u32 altera_mi = 0x6e;
 167         const u32 id = scan_mgr_get_fpga_id();
 168
 169         const u32 lsb = id & 0x00000001;
 170         const u32 mi = (id >> 1) & 0x000007ff;
 171         const u32 pn = (id >> 12) & 0x0000ffff;
 172         const u32 version = (id >> 28) & 0x0000000f;
 173         int i;
 174
 175         if ((mi != altera_mi) || (lsb != 1)) {
 176                 printf("FPGA:  Not Altera chip ID\n");
 177                 return -EINVAL;
 178         }
 179
 180         for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
 181                 if (pn == socfpga_fpga_model[i].pn)
 182                         break;
 183
 184         if (i == ARRAY_SIZE(socfpga_fpga_model)) {
 185                 printf("FPGA:  Unknown Altera chip, ID 0x%08x\n", id);
 186                 return -EINVAL;
 187         }
 188
 189         if (print_id)
 190                 printf("FPGA:  Altera %s, version 0x%01x\n",
 191                        socfpga_fpga_model[i].name, version);
 192         return i;
 193 }
 194
 195 /*
 196  * Print CPU information
 197  */
 198 #if defined(CONFIG_DISPLAY_CPUINFO)
 199 int print_cpuinfo(void)
 200 {
 201         const u32 bsel =
 202                 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
 203
 204         puts("CPU:   Altera SoCFPGA Platform\n");
 205         socfpga_fpga_id(1);
 206
 207         printf("BOOT:  %s\n", bsel_str[bsel].name);
 208         return 0;
 209 }
 210 #endif
 211
 212 #ifdef CONFIG_ARCH_MISC_INIT
 213 int arch_misc_init(void)
 214 {
 215         const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 216         const int fpga_id = socfpga_fpga_id(0);
 217         env_set("bootmode", bsel_str[bsel].mode);
 218         if (fpga_id >= 0)
 219                 env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
 220         return socfpga_eth_reset();
 221 }
 222 #endif
 223
 224 /*
 225  * Convert all NIC-301 AMBA slaves from secure to non-secure
 226  */
 227 static void socfpga_nic301_slave_ns(void)
 228 {
 229         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 230         writel(0x1, &nic301_regs->hps2fpgaregs);
 231         writel(0x1, &nic301_regs->acp);
 232         writel(0x1, &nic301_regs->rom);
 233         writel(0x1, &nic301_regs->ocram);
 234         writel(0x1, &nic301_regs->sdrdata);
 235 }
 236
 237 static u32 iswgrp_handoff[8];
 238
 239 int arch_early_init_r(void)
 240 {
 241         int i;
 242
 243         /*
 244          * Write magic value into magic register to unlock support for
 245          * issuing warm reset. The ancient kernel code expects this
 246          * value to be written into the register by the bootloader, so
 247          * to support that old code, we write it here instead of in the
 248          * reset_cpu() function just before resetting the CPU.
 249          */
 250         writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
 251
 252         for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
 253                 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
 254
 255         socfpga_bridges_reset(1);
 256
 257         socfpga_nic301_slave_ns();
 258
 259         /*
 260          * Private components security:
 261          * U-Boot : configure private timer, global timer and cpu component
 262          * access as non secure for kernel stage (as required by Linux)
 263          */
 264         setbits_le32(&scu_regs->sacr, 0xfff);
 265
 266         /* Configure the L2 controller to make SDRAM start at 0 */
 267 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 268         writel(0x2, &nic301_regs->remap);
 269 #else
 270         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
 271         writel(0x1, &pl310->pl310_addr_filter_start);
 272 #endif
 273
 274         /* Add device descriptor to FPGA device table */
 275         socfpga_fpga_add();
 276
 277 #ifdef CONFIG_DESIGNWARE_SPI
 278         /* Get Designware SPI controller out of reset */
 279         socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
 280         socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
 281 #endif
 282
 283 #ifdef CONFIG_NAND_DENALI
 284         socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
 285 #endif
 286
 287         return 0;
 288 }
 289
 290 #ifndef CONFIG_SPL_BUILD
 291 static struct socfpga_reset_manager *reset_manager_base =
 292         (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
 293 static struct socfpga_sdr_ctrl *sdr_ctrl =
 294         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 295
 296 static void socfpga_sdram_apply_static_cfg(void)
 297 {
 298         const u32 applymask = 0x8;
 299         u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
 300
 301         /*
 302          * SDRAM staticcfg register specific:
 303          * When applying the register setting, the CPU must not access
 304          * SDRAM. Luckily for us, we can abuse i-cache here to help us
 305          * circumvent the SDRAM access issue. The idea is to make sure
 306          * that the code is in one full i-cache line by branching past
 307          * it and back. Once it is in the i-cache, we execute the core
 308          * of the code and apply the register settings.
 309          *
 310          * The code below uses 7 instructions, while the Cortex-A9 has
 311          * 32-byte cachelines, thus the limit is 8 instructions total.
 312          */
 313         asm volatile(
 314                 ".align 5                       \n"
 315                 "       b       2f              \n"
 316                 "1:     str     %0,     [%1]    \n"
 317                 "       dsb                     \n"
 318                 "       isb                     \n"
 319                 "       b       3f              \n"
 320                 "2:     b       1b              \n"
 321                 "3:     nop                     \n"
 322         : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
 323 }
 324
 325 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 326 {
 327         if (argc != 2)
 328                 return CMD_RET_USAGE;
 329
 330         argv++;
 331
 332         switch (*argv[0]) {
 333         case 'e':       /* Enable */
 334                 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
 335                 socfpga_sdram_apply_static_cfg();
 336                 writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
 337                 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
 338                 writel(iswgrp_handoff[1], &nic301_regs->remap);
 339                 break;
 340         case 'd':       /* Disable */
 341                 writel(0, &sysmgr_regs->fpgaintfgrp_module);
 342                 writel(0, &sdr_ctrl->fpgaport_rst);
 343                 socfpga_sdram_apply_static_cfg();
 344                 writel(0, &reset_manager_base->brg_mod_reset);
 345                 writel(1, &nic301_regs->remap);
 346                 break;
 347         default:
 348                 return CMD_RET_USAGE;
 349         }
 350
 351         return 0;
 352 }
 353
 354 U_BOOT_CMD(
 355         bridge, 2, 1, do_bridge,
 356         "SoCFPGA HPS FPGA bridge control",
 357         "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 358         "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 359         ""
 360 );
 361 #endif