1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
14 #include <asm/arch/reset_manager.h>
15 #include <asm/arch/system_manager.h>
16 #include <asm/arch/misc.h>
17 #include <asm/pl310.h>
18 #include <linux/libfdt.h>
20 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 static struct socfpga_system_manager *sysmgr_regs =
25 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
28 * DesignWare Ethernet initialization
30 #ifdef CONFIG_ETH_DESIGNWARE
32 static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
39 if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii"))
40 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
41 else if (!strcmp(phymode, "rgmii"))
42 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
43 else if (!strcmp(phymode, "rmii"))
44 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
48 clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
49 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
55 static int socfpga_set_phymode(void)
57 const void *fdt = gd->fdt_blob;
58 struct fdtdec_phandle_args args;
61 int nodes[2]; /* Max. 3 GMACs */
65 count = fdtdec_find_aliases_for_id(fdt, "ethernet",
66 COMPAT_ALTERA_SOCFPGA_DWMAC,
67 nodes, ARRAY_SIZE(nodes));
68 for (i = 0; i < count; i++) {
73 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
76 if (ret || args.args_count != 1) {
77 debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
81 gmac_index = args.args[0] - EMAC0_RESET;
83 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
84 ret = socfpga_phymode_setup(gmac_index, phy_mode);
86 debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
94 static int socfpga_set_phymode(void)
101 * Print CPU information
103 #if defined(CONFIG_DISPLAY_CPUINFO)
104 int print_cpuinfo(void)
106 puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
112 #ifdef CONFIG_ARCH_MISC_INIT
113 int arch_misc_init(void)
115 char qspi_string[13];
117 sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
118 env_set("qspi_clock", qspi_string);
120 socfpga_set_phymode();
125 int arch_early_init_r(void)
130 void do_bridge_reset(int enable)
132 socfpga_bridges_reset(enable);