2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fpga_manager.h>
11 #include <asm/arch/reset_manager.h>
12 #include <asm/arch/system_manager.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 static const struct socfpga_reset_manager *reset_manager_base =
17 (void *)SOCFPGA_RSTMGR_ADDRESS;
18 static struct socfpga_system_manager *sysmgr_regs =
19 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
21 /* Assert or de-assert SoCFPGA reset manager reset. */
22 void socfpga_per_reset(u32 reset, int set)
26 if (RSTMGR_BANK(reset) == 0)
27 reg = &reset_manager_base->mpu_mod_reset;
28 else if (RSTMGR_BANK(reset) == 1)
29 reg = &reset_manager_base->per_mod_reset;
30 else if (RSTMGR_BANK(reset) == 2)
31 reg = &reset_manager_base->per2_mod_reset;
32 else if (RSTMGR_BANK(reset) == 3)
33 reg = &reset_manager_base->brg_mod_reset;
34 else if (RSTMGR_BANK(reset) == 4)
35 reg = &reset_manager_base->misc_mod_reset;
36 else /* Invalid reset register, do nothing */
40 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
42 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
46 * Assert reset on every peripheral but L4WD0.
47 * Watchdog must be kept intact to prevent glitches
50 void socfpga_per_reset_all(void)
52 const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
54 writel(~l4wd0, &reset_manager_base->per_mod_reset);
55 writel(0xffffffff, &reset_manager_base->per2_mod_reset);
59 * Write the reset manager register to cause reset
61 void reset_cpu(ulong addr)
63 /* request a warm reset */
64 writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
65 &reset_manager_base->ctrl);
67 * infinite loop here as watchdog will trigger and reset
75 * Release peripherals from reset based on handoff
77 void reset_deassert_peripherals_handoff(void)
79 writel(0, &reset_manager_base->per_mod_reset);
82 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
83 void socfpga_bridges_reset(int enable)
85 /* For SoCFPGA-VT, this is NOP. */
89 #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
90 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08
91 #define L3REGS_REMAP_OCRAM_MASK 0x01
93 void socfpga_bridges_reset(int enable)
95 const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
96 L3REGS_REMAP_HPS2FPGA_MASK |
97 L3REGS_REMAP_OCRAM_MASK;
101 writel(0xffffffff, &reset_manager_base->brg_mod_reset);
103 writel(0, &sysmgr_regs->iswgrp_handoff[0]);
104 writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
106 /* Check signal from FPGA. */
107 if (!fpgamgr_test_fpga_ready()) {
108 /* FPGA not ready, do nothing. */
109 printf("%s: FPGA not ready, aborting.\n", __func__);
114 writel(0, &reset_manager_base->brg_mod_reset);
116 /* Remap the bridges into memory map */
117 writel(l3mask, SOCFPGA_L3REGS_ADDRESS);