2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/reset_manager.h>
11 #include <asm/arch/fpga_manager.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 static const struct socfpga_reset_manager *reset_manager_base =
16 (void *)SOCFPGA_RSTMGR_ADDRESS;
18 /* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
19 void socfpga_watchdog_reset(void)
21 /* assert reset for watchdog */
22 setbits_le32(&reset_manager_base->per_mod_reset,
23 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
25 /* deassert watchdog from reset (watchdog in not running state) */
26 clrbits_le32(&reset_manager_base->per_mod_reset,
27 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
31 * Write the reset manager register to cause reset
33 void reset_cpu(ulong addr)
35 /* request a warm reset */
36 writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
37 &reset_manager_base->ctrl);
39 * infinite loop here as watchdog will trigger and reset
47 * Release peripherals from reset based on handoff
49 void reset_deassert_peripherals_handoff(void)
51 writel(0, &reset_manager_base->per_mod_reset);
54 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
55 void socfpga_bridges_reset(int enable)
57 /* For SoCFPGA-VT, this is NOP. */
61 #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
62 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08
63 #define L3REGS_REMAP_OCRAM_MASK 0x01
65 void socfpga_bridges_reset(int enable)
67 const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
68 L3REGS_REMAP_HPS2FPGA_MASK |
69 L3REGS_REMAP_OCRAM_MASK;
73 writel(0xffffffff, &reset_manager_base->brg_mod_reset);
75 /* Check signal from FPGA. */
76 if (fpgamgr_poll_fpga_ready()) {
77 /* FPGA not ready. Wait for watchdog timeout. */
78 printf("%s: fpga not ready, hanging.\n", __func__);
83 writel(0, &reset_manager_base->brg_mod_reset);
85 /* Remap the bridges into memory map */
86 writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
91 /* Change the reset state for EMAC 0 and EMAC 1 */
92 void socfpga_emac_reset(int enable)
94 const void *reset = &reset_manager_base->per_mod_reset;
97 setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0)));
98 setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1)));
100 #if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
101 clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0)));
102 #elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
103 clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1)));
108 /* SPI Master enable (its held in reset by the preloader) */
109 void socfpga_spim_enable(void)
111 const void *reset = &reset_manager_base->per_mod_reset;
113 clrbits_le32(reset, (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM0))) |
114 (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM1))));
117 /* Bring UART0 out of reset. */
118 void socfpga_uart0_enable(void)
120 const void *reset = &reset_manager_base->per_mod_reset;
122 clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(UART0)));
125 /* Bring SDRAM controller out of reset. */
126 void socfpga_sdram_enable(void)
128 const void *reset = &reset_manager_base->per_mod_reset;
130 clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(SDR)));
133 /* Bring OSC1 timer out of reset. */
134 void socfpga_osc1timer_enable(void)
136 const void *reset = &reset_manager_base->per_mod_reset;
138 clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(OSC1TIMER0)));