2 * Copyright (C) 2016-2017 Intel Corporation
4 * SPDX-License-Identifier: GPL-2.0
8 #include <asm/arch/fpga_manager.h>
9 #include <asm/arch/misc.h>
10 #include <asm/arch/reset_manager.h>
11 #include <asm/arch/system_manager.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 static const struct socfpga_reset_manager *reset_manager_base =
20 (void *)SOCFPGA_RSTMGR_ADDRESS;
21 static const struct socfpga_system_manager *sysmgr_regs =
22 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
24 #define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | \
25 ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK | \
26 ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK | \
27 ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK | \
28 ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \
29 ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
31 void socfpga_reset_uart(int assert)
33 unsigned int com_port;
35 com_port = uart_com_port(gd->fdt_blob);
37 if (com_port == SOCFPGA_UART1_ADDRESS)
38 socfpga_per_reset(SOCFPGA_RESET(UART1), assert);
39 else if (com_port == SOCFPGA_UART0_ADDRESS)
40 socfpga_per_reset(SOCFPGA_RESET(UART0), assert);
43 static const u32 per0fpgamasks[] = {
44 ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
45 ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,
46 ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
47 ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK,
48 ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
49 ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK,
55 ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
56 ALT_RSTMGR_PER0MODRST_NAND_SET_MSK,
57 ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
58 ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK,
59 ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK |
60 ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK,
61 ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK,
62 ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK,
63 ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK,
64 ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK,
65 0, /* uart0 per1mod */
66 0, /* uart1 per1mod */
69 static const u32 per1fpgamasks[] = {
70 0, /* emac0 per0mod */
71 0, /* emac1 per0mod */
72 0, /* emac2 per0mod */
73 ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK,
74 ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK,
75 ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK, /* i2c0_emac */
76 ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK, /* i2c1_emac */
77 ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK, /* i2c2_emac */
80 0, /* sdmmc per0mod */
81 0, /* spim0 per0mod */
82 0, /* spim1 per0mod */
83 0, /* spis0 per0mod */
84 0, /* spis1 per0mod */
85 ALT_RSTMGR_PER1MODRST_UART0_SET_MSK,
86 ALT_RSTMGR_PER1MODRST_UART1_SET_MSK,
95 static const struct bridge_cfg bridge_cfg_tbl[] = {
97 COMPAT_ALTERA_SOCFPGA_H2F_BRG,
98 ALT_SYSMGR_NOC_H2F_SET_MSK,
99 ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
102 COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
103 ALT_SYSMGR_NOC_LWH2F_SET_MSK,
104 ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
107 COMPAT_ALTERA_SOCFPGA_F2H_BRG,
108 ALT_SYSMGR_NOC_F2H_SET_MSK,
109 ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
112 COMPAT_ALTERA_SOCFPGA_F2SDR0,
113 ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
114 ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
117 COMPAT_ALTERA_SOCFPGA_F2SDR1,
118 ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
119 ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
122 COMPAT_ALTERA_SOCFPGA_F2SDR2,
123 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
124 ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
128 /* Disable the watchdog (toggle reset to watchdog) */
129 void socfpga_watchdog_disable(void)
131 /* assert reset for watchdog */
132 setbits_le32(&reset_manager_base->per1modrst,
133 ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
136 /* Release NOC ddr scheduler from reset */
137 void socfpga_reset_deassert_noc_ddr_scheduler(void)
139 clrbits_le32(&reset_manager_base->brgmodrst,
140 ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
143 /* Check whether Watchdog in reset state? */
144 int socfpga_is_wdt_in_reset(void)
148 val = readl(&reset_manager_base->per1modrst);
149 val &= ALT_RSTMGR_PER1MODRST_WD0_SET_MSK;
151 /* return 0x1 if watchdog in reset */
155 /* emacbase: base address of emac to enable/disable reset
156 * state: 0 - disable reset, !0 - enable reset
158 void socfpga_emac_manage_reset(ulong emacbase, u32 state)
164 case SOCFPGA_EMAC0_ADDRESS:
165 eccmask = ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK;
166 emacmask = ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK;
168 case SOCFPGA_EMAC1_ADDRESS:
169 eccmask = ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK;
170 emacmask = ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK;
172 case SOCFPGA_EMAC2_ADDRESS:
173 eccmask = ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK;
174 emacmask = ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK;
177 pr_err("emac base address unexpected! %lx", emacbase);
183 /* Enable ECC OCP first */
184 setbits_le32(&reset_manager_base->per0modrst, eccmask);
185 setbits_le32(&reset_manager_base->per0modrst, emacmask);
187 /* Disable ECC OCP first */
188 clrbits_le32(&reset_manager_base->per0modrst, emacmask);
189 clrbits_le32(&reset_manager_base->per0modrst, eccmask);
193 static int get_bridge_init_val(const void *blob, int compat_id)
197 node = fdtdec_next_compatible(blob, 0, compat_id);
201 return fdtdec_get_uint(blob, node, "init-val", 0);
204 /* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
205 int socfpga_reset_deassert_bridges_handoff(void)
207 u32 mask_noc = 0, mask_rstmgr = 0;
210 for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
211 if (get_bridge_init_val(gd->fdt_blob,
212 bridge_cfg_tbl[i].compat_id)) {
213 mask_noc |= bridge_cfg_tbl[i].mask_noc;
214 mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
218 /* clear idle request to all bridges */
219 setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
221 /* Release bridges from reset state per handoff value */
222 clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
224 /* Poll until all idleack to 0, timeout at 1000ms */
225 return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
229 void socfpga_reset_assert_fpga_connected_peripherals(void)
233 u32 fpga_pinux_addr = SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS;
236 for (i = 0; i < ARRAY_SIZE(per1fpgamasks); i++) {
237 if (readl(fpga_pinux_addr)) {
238 mask0 |= per0fpgamasks[i];
239 mask1 |= per1fpgamasks[i];
241 fpga_pinux_addr += sizeof(u32);
244 setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK);
245 setbits_le32(&reset_manager_base->per1modrst, mask1);
246 setbits_le32(&reset_manager_base->per0modrst, mask0);
249 /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
250 void socfpga_reset_deassert_osc1wd0(void)
252 clrbits_le32(&reset_manager_base->per1modrst,
253 ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
257 * Assert or de-assert SoCFPGA reset manager reset.
259 void socfpga_per_reset(u32 reset, int set)
262 u32 rstmgr_bank = RSTMGR_BANK(reset);
264 switch (rstmgr_bank) {
266 reg = &reset_manager_base->mpumodrst;
269 reg = &reset_manager_base->per0modrst;
272 reg = &reset_manager_base->per1modrst;
275 reg = &reset_manager_base->brgmodrst;
278 reg = &reset_manager_base->sysmodrst;
286 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
288 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
292 * Assert reset on every peripheral but L4WD0.
293 * Watchdog must be kept intact to prevent glitches
295 * For the Arria10, we disable all the peripherals except L4 watchdog0,
296 * L4 Timer 0, and ECC.
298 void socfpga_per_reset_all(void)
300 const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
301 (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
302 unsigned mask_ecc_ocp =
303 ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
304 ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
305 ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
306 ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
307 ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
308 ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
309 ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
310 ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
312 /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
313 writel(~l4wd0, &reset_manager_base->per1modrst);
314 setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
316 /* Finally disable the ECC_OCP */
317 setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
320 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
321 int socfpga_bridges_reset(void)
323 /* For SoCFPGA-VT, this is NOP. */
327 int socfpga_bridges_reset(void)
331 /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
333 /* set idle request to all bridges */
334 writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
335 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
336 ALT_SYSMGR_NOC_F2H_SET_MSK |
337 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
338 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
339 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
340 &sysmgr_regs->noc_idlereq_set);
342 /* Enable the NOC timeout */
343 writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
345 /* Poll until all idleack to 1 */
346 ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
347 ALT_SYSMGR_NOC_H2F_SET_MSK |
348 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
349 ALT_SYSMGR_NOC_F2H_SET_MSK |
350 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
351 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
352 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
357 /* Poll until all idlestatus to 1 */
358 ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
359 ALT_SYSMGR_NOC_H2F_SET_MSK |
360 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
361 ALT_SYSMGR_NOC_F2H_SET_MSK |
362 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
363 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
364 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
369 /* Put all bridges (except NOR DDR scheduler) into reset state */
370 setbits_le32(&reset_manager_base->brgmodrst,
371 (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
372 ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
373 ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
374 ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
375 ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
376 ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
378 /* Disable NOC timeout */
379 writel(0, &sysmgr_regs->noc_timeout);