2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fpga_manager.h>
11 #include <asm/arch/reset_manager.h>
12 #include <asm/arch/system_manager.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 static const struct socfpga_reset_manager *reset_manager_base =
17 (void *)SOCFPGA_RSTMGR_ADDRESS;
18 static const struct socfpga_system_manager *sysmgr_regs =
19 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
21 /* Assert or de-assert SoCFPGA reset manager reset. */
22 void socfpga_per_reset(u32 reset, int set)
25 u32 rstmgr_bank = RSTMGR_BANK(reset);
27 switch (rstmgr_bank) {
29 reg = &reset_manager_base->mpu_mod_reset;
32 reg = &reset_manager_base->per_mod_reset;
35 reg = &reset_manager_base->per2_mod_reset;
38 reg = &reset_manager_base->brg_mod_reset;
41 reg = &reset_manager_base->misc_mod_reset;
49 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
51 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
55 * Assert reset on every peripheral but L4WD0.
56 * Watchdog must be kept intact to prevent glitches
59 void socfpga_per_reset_all(void)
61 const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
63 writel(~l4wd0, &reset_manager_base->per_mod_reset);
64 writel(0xffffffff, &reset_manager_base->per2_mod_reset);
68 * Release peripherals from reset based on handoff
70 void reset_deassert_peripherals_handoff(void)
72 writel(0, &reset_manager_base->per_mod_reset);
75 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
76 void socfpga_bridges_reset(int enable)
78 /* For SoCFPGA-VT, this is NOP. */
83 #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
84 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08
85 #define L3REGS_REMAP_OCRAM_MASK 0x01
87 void socfpga_bridges_reset(int enable)
89 const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
90 L3REGS_REMAP_HPS2FPGA_MASK |
91 L3REGS_REMAP_OCRAM_MASK;
95 writel(0xffffffff, &reset_manager_base->brg_mod_reset);
97 writel(0, &sysmgr_regs->iswgrp_handoff[0]);
98 writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);
100 /* Check signal from FPGA. */
101 if (!fpgamgr_test_fpga_ready()) {
102 /* FPGA not ready, do nothing. We allow system to boot
103 * without FPGA ready. So, return 0 instead of error. */
104 printf("%s: FPGA not ready, aborting.\n", __func__);
109 writel(0, &reset_manager_base->brg_mod_reset);
111 /* Remap the bridges into memory map */
112 writel(l3mask, SOCFPGA_L3REGS_ADDRESS);