2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/u-boot.h>
11 #include <asm/utils.h>
13 #include <asm/arch/reset_manager.h>
15 #include <asm/arch/system_manager.h>
16 #include <asm/arch/freeze_controller.h>
17 #include <asm/arch/clock_manager.h>
18 #include <asm/arch/scan_manager.h>
19 #include <asm/arch/sdram.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 static struct pl310_regs *const pl310 =
24 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
26 void board_init_f(ulong dummy)
28 struct socfpga_system_manager *sysmgr_regs =
29 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
32 * First C code to run. Clear fake OCRAM ECC first as SBE
33 * and DBE might triggered during power on
35 reg = readl(&sysmgr_regs->eccgrp_ocram);
36 if (reg & SYSMGR_ECC_OCRAM_SERR)
37 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
38 &sysmgr_regs->eccgrp_ocram);
39 if (reg & SYSMGR_ECC_OCRAM_DERR)
40 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
41 &sysmgr_regs->eccgrp_ocram);
43 memset(__bss_start, 0, __bss_end - __bss_start);
45 /* Remap SDRAM to 0x0 */
46 writel(0x1, &pl310->pl310_addr_filter_start);
48 board_init_r(NULL, 0);
51 u32 spl_boot_device(void)
53 return BOOT_DEVICE_RAM;
57 * Board initialization after bss clearance
59 void spl_board_init(void)
61 unsigned long sdram_size;
62 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
63 const struct cm_config *cm_default_cfg = cm_get_default_config();
66 debug("Freezing all I/O banks\n");
67 /* freeze all IO banks */
68 sys_mgr_frzctrl_freeze_req();
70 socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
71 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
72 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
76 debug("Reconfigure Clock Manager\n");
77 /* reconfigure the PLLs */
78 cm_basic_init(cm_default_cfg);
80 /* Enable bootrom to configure IOs. */
81 sysmgr_config_warmrstcfgio(1);
83 /* configure the IOCSR / IO buffer settings */
84 if (scan_mgr_configure_iocsr())
87 sysmgr_config_warmrstcfgio(0);
89 /* configure the pin muxing through system manager */
90 sysmgr_config_warmrstcfgio(1);
92 sysmgr_config_warmrstcfgio(0);
94 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
96 /* de-assert reset for peripherals and bridges based on handoff */
97 reset_deassert_peripherals_handoff();
99 debug("Unfreezing/Thaw all I/O banks\n");
100 /* unfreeze / thaw all IO banks */
101 sys_mgr_frzctrl_thaw_req();
103 /* enable console uart printing */
104 preloader_console_init();
106 if (sdram_mmr_init_full(0xffffffff) != 0) {
107 puts("SDRAM init failed.\n");
111 debug("SDRAM: Calibrating PHY\n");
112 /* SDRAM calibration */
113 if (sdram_calibration_full() == 0) {
114 puts("SDRAM calibration failed.\n");
118 sdram_size = sdram_calculate_size();
119 debug("SDRAM: %ld MiB\n", sdram_size >> 20);
121 /* Sanity check ensure correct SDRAM size specified */
122 if (get_ram_size(0, sdram_size) != sdram_size) {
123 puts("SDRAM size check failed!\n");