1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
8 #include <asm/arch/clock_manager.h>
10 #include <asm/arch/handoff_s10.h>
11 #include <asm/arch/system_manager.h>
13 static const struct socfpga_system_manager *sysmgr_regs =
14 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
16 const struct cm_config * const cm_get_default_config(void)
18 struct cm_config *cm_handoff_cfg = (struct cm_config *)
19 (S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
20 u32 *conversion = (u32 *)cm_handoff_cfg;
22 u32 handoff_clk = readl(S10_HANDOFF_CLOCK);
24 if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) {
25 writel(swab32(handoff_clk), S10_HANDOFF_CLOCK);
26 for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
27 conversion[i] = swab32(conversion[i]);
28 return cm_handoff_cfg;
29 } else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
30 return cm_handoff_cfg;
36 const unsigned int cm_get_osc_clk_hz(void)
38 #ifdef CONFIG_SPL_BUILD
39 u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
41 writel(clock, &sysmgr_regs->boot_scratch_cold1);
43 return readl(&sysmgr_regs->boot_scratch_cold1);
46 const unsigned int cm_get_intosc_clk_hz(void)
48 return CLKMGR_INTOSC_HZ;
51 const unsigned int cm_get_fpga_clk_hz(void)
53 #ifdef CONFIG_SPL_BUILD
54 u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
56 writel(clock, &sysmgr_regs->boot_scratch_cold2);
58 return readl(&sysmgr_regs->boot_scratch_cold2);