3 * Kamil Lulko, <kamil.lulko@gmail.com>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/stm32.h>
14 #include <asm/arch/stm32_periph.h>
16 #define RCC_CR_HSION (1 << 0)
17 #define RCC_CR_HSEON (1 << 16)
18 #define RCC_CR_HSERDY (1 << 17)
19 #define RCC_CR_HSEBYP (1 << 18)
20 #define RCC_CR_CSSON (1 << 19)
21 #define RCC_CR_PLLON (1 << 24)
22 #define RCC_CR_PLLRDY (1 << 25)
24 #define RCC_PLLCFGR_PLLM_MASK 0x3F
25 #define RCC_PLLCFGR_PLLN_MASK 0x7FC0
26 #define RCC_PLLCFGR_PLLP_MASK 0x30000
27 #define RCC_PLLCFGR_PLLQ_MASK 0xF000000
28 #define RCC_PLLCFGR_PLLSRC (1 << 22)
29 #define RCC_PLLCFGR_PLLN_SHIFT 6
30 #define RCC_PLLCFGR_PLLP_SHIFT 16
31 #define RCC_PLLCFGR_PLLQ_SHIFT 24
33 #define RCC_CFGR_AHB_PSC_MASK 0xF0
34 #define RCC_CFGR_APB1_PSC_MASK 0x1C00
35 #define RCC_CFGR_APB2_PSC_MASK 0xE000
36 #define RCC_CFGR_SW0 (1 << 0)
37 #define RCC_CFGR_SW1 (1 << 1)
38 #define RCC_CFGR_SW_MASK 0x3
39 #define RCC_CFGR_SW_HSI 0
40 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
41 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
42 #define RCC_CFGR_SWS0 (1 << 2)
43 #define RCC_CFGR_SWS1 (1 << 3)
44 #define RCC_CFGR_SWS_MASK 0xC
45 #define RCC_CFGR_SWS_HSI 0
46 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
47 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
48 #define RCC_CFGR_HPRE_SHIFT 4
49 #define RCC_CFGR_PPRE1_SHIFT 10
50 #define RCC_CFGR_PPRE2_SHIFT 13
52 #define RCC_APB1ENR_PWREN (1 << 28)
55 * RCC USART specific definitions
57 #define RCC_ENR_USART1EN (1 << 4)
58 #define RCC_ENR_USART2EN (1 << 17)
59 #define RCC_ENR_USART3EN (1 << 18)
60 #define RCC_ENR_USART6EN (1 << 5)
62 #define PWR_CR_VOS0 (1 << 14)
63 #define PWR_CR_VOS1 (1 << 15)
64 #define PWR_CR_VOS_MASK 0xC000
65 #define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
66 #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
67 #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
69 #define FLASH_ACR_WS(n) n
70 #define FLASH_ACR_PRFTEN (1 << 8)
71 #define FLASH_ACR_ICEN (1 << 9)
72 #define FLASH_ACR_DCEN (1 << 10)
88 #define AHB_PSC_16 0xB
89 #define AHB_PSC_64 0xC
90 #define AHB_PSC_128 0xD
91 #define AHB_PSC_256 0xE
92 #define AHB_PSC_512 0xF
98 #define APB_PSC_16 0x7
100 #if !defined(CONFIG_STM32_HSE_HZ)
101 #error "CONFIG_STM32_HSE_HZ not defined!"
103 #if (CONFIG_STM32_HSE_HZ == 8000000)
104 #if (CONFIG_SYS_CLK_FREQ == 180000000)
106 struct pll_psc sys_pll_psc = {
111 .ahb_psc = AHB_PSC_1,
112 .apb1_psc = APB_PSC_4,
113 .apb2_psc = APB_PSC_2
116 /* default 168 MHz */
117 struct pll_psc sys_pll_psc = {
122 .ahb_psc = AHB_PSC_1,
123 .apb1_psc = APB_PSC_4,
124 .apb2_psc = APB_PSC_2
128 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
132 int configure_clocks(void)
134 /* Reset RCC configuration */
135 setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
136 writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
137 clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
139 writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
140 clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
141 writel(0, &STM32_RCC->cir); /* Disable all interrupts */
143 /* Configure for HSE+PLL operation */
144 setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
145 while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
148 /* Enable high performance mode, System frequency up to 180 MHz */
149 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
150 writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
152 setbits_le32(&STM32_RCC->cfgr, ((
153 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
154 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
155 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
157 writel(sys_pll_psc.pll_m
158 | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
159 | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
160 | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
161 &STM32_RCC->pllcfgr);
162 setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
164 setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
166 while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
169 /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
170 writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
171 | FLASH_ACR_DCEN, &STM32_FLASH->acr);
173 clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
174 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
176 while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
183 unsigned long clock_get(enum clock clck)
187 /* Prescaler table lookups for clock computation */
188 u8 ahb_psc_table[16] = {
189 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
191 u8 apb_psc_table[8] = {
192 0, 0, 0, 0, 1, 2, 3, 4
195 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
197 u16 pllm, plln, pllp;
198 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
199 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
200 >> RCC_PLLCFGR_PLLN_SHIFT);
201 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
202 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
203 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
211 shift = ahb_psc_table[(
212 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
213 >> RCC_CFGR_HPRE_SHIFT)];
214 return sysclk >>= shift;
217 shift = apb_psc_table[(
218 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
219 >> RCC_CFGR_PPRE1_SHIFT)];
220 return sysclk >>= shift;
223 shift = apb_psc_table[(
224 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
225 >> RCC_CFGR_PPRE2_SHIFT)];
226 return sysclk >>= shift;
234 void clock_setup(int peripheral)
236 switch (peripheral) {
237 case USART1_CLOCK_CFG:
238 setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);