3 * Vikas Manocha, <vikas.manocha@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/rcc.h>
11 #include <asm/arch/stm32.h>
12 #include <asm/arch/stm32_periph.h>
14 #define RCC_CR_HSION (1 << 0)
15 #define RCC_CR_HSEON (1 << 16)
16 #define RCC_CR_HSERDY (1 << 17)
17 #define RCC_CR_HSEBYP (1 << 18)
18 #define RCC_CR_CSSON (1 << 19)
19 #define RCC_CR_PLLON (1 << 24)
20 #define RCC_CR_PLLRDY (1 << 25)
22 #define RCC_PLLCFGR_PLLM_MASK 0x3F
23 #define RCC_PLLCFGR_PLLN_MASK 0x7FC0
24 #define RCC_PLLCFGR_PLLP_MASK 0x30000
25 #define RCC_PLLCFGR_PLLQ_MASK 0xF000000
26 #define RCC_PLLCFGR_PLLSRC (1 << 22)
27 #define RCC_PLLCFGR_PLLM_SHIFT 0
28 #define RCC_PLLCFGR_PLLN_SHIFT 6
29 #define RCC_PLLCFGR_PLLP_SHIFT 16
30 #define RCC_PLLCFGR_PLLQ_SHIFT 24
32 #define RCC_CFGR_AHB_PSC_MASK 0xF0
33 #define RCC_CFGR_APB1_PSC_MASK 0x1C00
34 #define RCC_CFGR_APB2_PSC_MASK 0xE000
35 #define RCC_CFGR_SW0 (1 << 0)
36 #define RCC_CFGR_SW1 (1 << 1)
37 #define RCC_CFGR_SW_MASK 0x3
38 #define RCC_CFGR_SW_HSI 0
39 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
40 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
41 #define RCC_CFGR_SWS0 (1 << 2)
42 #define RCC_CFGR_SWS1 (1 << 3)
43 #define RCC_CFGR_SWS_MASK 0xC
44 #define RCC_CFGR_SWS_HSI 0
45 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
46 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
47 #define RCC_CFGR_HPRE_SHIFT 4
48 #define RCC_CFGR_PPRE1_SHIFT 10
49 #define RCC_CFGR_PPRE2_SHIFT 13
51 #define RCC_APB1ENR_PWREN (1 << 28)
54 * RCC USART specific definitions
56 #define RCC_ENR_USART1EN (1 << 4)
57 #define RCC_ENR_USART2EN (1 << 17)
58 #define RCC_ENR_USART3EN (1 << 18)
59 #define RCC_ENR_USART6EN (1 << 5)
62 * Offsets of some PWR registers
64 #define PWR_CR1_ODEN (1 << 16)
65 #define PWR_CR1_ODSWEN (1 << 17)
66 #define PWR_CSR1_ODRDY (1 << 16)
67 #define PWR_CSR1_ODSWRDY (1 << 17)
71 * RCC GPIO specific definitions
73 #define RCC_ENR_GPIO_A_EN (1 << 0)
74 #define RCC_ENR_GPIO_B_EN (1 << 1)
75 #define RCC_ENR_GPIO_C_EN (1 << 2)
76 #define RCC_ENR_GPIO_D_EN (1 << 3)
77 #define RCC_ENR_GPIO_E_EN (1 << 4)
78 #define RCC_ENR_GPIO_F_EN (1 << 5)
79 #define RCC_ENR_GPIO_G_EN (1 << 6)
80 #define RCC_ENR_GPIO_H_EN (1 << 7)
81 #define RCC_ENR_GPIO_I_EN (1 << 8)
82 #define RCC_ENR_GPIO_J_EN (1 << 9)
83 #define RCC_ENR_GPIO_K_EN (1 << 10)
99 #define AHB_PSC_16 0xB
100 #define AHB_PSC_64 0xC
101 #define AHB_PSC_128 0xD
102 #define AHB_PSC_256 0xE
103 #define AHB_PSC_512 0xF
106 #define APB_PSC_2 0x4
107 #define APB_PSC_4 0x5
108 #define APB_PSC_8 0x6
109 #define APB_PSC_16 0x7
111 #if !defined(CONFIG_STM32_HSE_HZ)
112 #error "CONFIG_STM32_HSE_HZ not defined!"
114 #if (CONFIG_STM32_HSE_HZ == 25000000)
115 #if (CONFIG_SYS_CLK_FREQ == 200000000)
117 struct pll_psc sys_pll_psc = {
122 .ahb_psc = AHB_PSC_1,
123 .apb1_psc = APB_PSC_4,
124 .apb2_psc = APB_PSC_2
128 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
132 int configure_clocks(void)
134 /* Reset RCC configuration */
135 setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
136 writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
137 clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
139 writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
140 clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
141 writel(0, &STM32_RCC->cir); /* Disable all interrupts */
143 /* Configure for HSE+PLL operation */
144 setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
145 while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
148 setbits_le32(&STM32_RCC->cfgr, ((
149 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
150 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
151 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
153 /* Configure the main PLL */
154 uint32_t pllcfgr = 0;
155 pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
156 pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
157 pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
158 pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
159 pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
160 writel(pllcfgr, &STM32_RCC->pllcfgr);
162 /* Enable the main PLL */
163 setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
164 while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
167 /* Enable high performance mode, System frequency up to 200 MHz */
168 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
169 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
171 while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
173 /* Enable the Over-drive switch */
174 setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
176 while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
179 stm32_flash_latency_cfg(5);
180 clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
181 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
183 while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
190 unsigned long clock_get(enum clock clck)
194 /* Prescaler table lookups for clock computation */
195 u8 ahb_psc_table[16] = {
196 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
198 u8 apb_psc_table[8] = {
199 0, 0, 0, 0, 1, 2, 3, 4
202 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
204 u16 pllm, plln, pllp;
205 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
206 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
207 >> RCC_PLLCFGR_PLLN_SHIFT);
208 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
209 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
210 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
218 shift = ahb_psc_table[(
219 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
220 >> RCC_CFGR_HPRE_SHIFT)];
221 return sysclk >>= shift;
224 shift = apb_psc_table[(
225 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
226 >> RCC_CFGR_PPRE1_SHIFT)];
227 return sysclk >>= shift;
230 shift = apb_psc_table[(
231 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
232 >> RCC_CFGR_PPRE2_SHIFT)];
233 return sysclk >>= shift;
242 void clock_setup(int peripheral)
244 switch (peripheral) {
245 case USART1_CLOCK_CFG:
246 setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN);
248 case GPIO_A_CLOCK_CFG:
249 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN);
251 case GPIO_B_CLOCK_CFG:
252 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN);
254 case GPIO_C_CLOCK_CFG:
255 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN);
257 case GPIO_D_CLOCK_CFG:
258 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN);
260 case GPIO_E_CLOCK_CFG:
261 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN);
263 case GPIO_F_CLOCK_CFG:
264 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN);
266 case GPIO_G_CLOCK_CFG:
267 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN);
269 case GPIO_H_CLOCK_CFG:
270 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN);
272 case GPIO_I_CLOCK_CFG:
273 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN);
275 case GPIO_J_CLOCK_CFG:
276 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN);
278 case GPIO_K_CLOCK_CFG:
279 setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN);