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   1 /*
   2  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+        BSD-3-Clause
   5  */
   6
   7 #ifndef _MACH_STM32_H_
   8 #define _MACH_STM32_H_
   9
  10 /*
  11  * Peripheral memory map
  12  * only address used before device tree parsing
  13  */
  14 #define STM32_RCC_BASE                  0x50000000
  15 #define STM32_PWR_BASE                  0x50001000
  16 #define STM32_DBGMCU_BASE               0x50081000
  17 #define STM32_TZC_BASE                  0x5C006000
  18 #define STM32_ETZPC_BASE                0x5C007000
  19 #define STM32_TAMP_BASE                 0x5C00A000
  20
  21 #define STM32_SYSRAM_BASE               0x2FFC0000
  22 #define STM32_SYSRAM_SIZE               SZ_256K
  23
  24 #define STM32_DDR_BASE                  0xC0000000
  25 #define STM32_DDR_SIZE                  SZ_1G
  26
  27 #ifndef __ASSEMBLY__
  28 /* enumerated used to identify the SYSCON driver instance */
  29 enum {
  30         STM32MP_SYSCON_UNKNOWN,
  31         STM32MP_SYSCON_STGEN,
  32 };
  33
  34 /*
  35  * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
  36  * - boot device = bit 8:4
  37  * - boot instance = bit 3:0
  38  */
  39 #define BOOT_TYPE_MASK          0xF0
  40 #define BOOT_TYPE_SHIFT         4
  41 #define BOOT_INSTANCE_MASK      0x0F
  42 #define BOOT_INSTANCE_SHIFT     0
  43
  44 enum boot_device {
  45         BOOT_FLASH_SD = 0x10,
  46         BOOT_FLASH_SD_1 = 0x11,
  47         BOOT_FLASH_SD_2 = 0x12,
  48         BOOT_FLASH_SD_3 = 0x13,
  49
  50         BOOT_FLASH_EMMC = 0x20,
  51         BOOT_FLASH_EMMC_1 = 0x21,
  52         BOOT_FLASH_EMMC_2 = 0x22,
  53         BOOT_FLASH_EMMC_3 = 0x23,
  54
  55         BOOT_FLASH_NAND = 0x30,
  56         BOOT_FLASH_NAND_FMC = 0x31,
  57
  58         BOOT_FLASH_NOR = 0x40,
  59         BOOT_FLASH_NOR_QSPI = 0x41,
  60
  61         BOOT_SERIAL_UART = 0x50,
  62         BOOT_SERIAL_UART_1 = 0x51,
  63         BOOT_SERIAL_UART_2 = 0x52,
  64         BOOT_SERIAL_UART_3 = 0x53,
  65         BOOT_SERIAL_UART_4 = 0x54,
  66         BOOT_SERIAL_UART_5 = 0x55,
  67         BOOT_SERIAL_UART_6 = 0x56,
  68         BOOT_SERIAL_UART_7 = 0x57,
  69         BOOT_SERIAL_UART_8 = 0x58,
  70
  71         BOOT_SERIAL_USB = 0x60,
  72         BOOT_SERIAL_USB_OTG = 0x62,
  73 };
  74
  75 /* TAMP registers */
  76 #define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * x)
  77 #define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(20)
  78
  79 #define TAMP_BOOT_MODE_MASK             GENMASK(15, 8)
  80 #define TAMP_BOOT_MODE_SHIFT            8
  81 #define TAMP_BOOT_DEVICE_MASK           GENMASK(7, 4)
  82 #define TAMP_BOOT_INSTANCE_MASK         GENMASK(3, 0)
  83
  84 #endif /* __ASSEMBLY__*/
  85 #endif /* _MACH_STM32_H_ */