4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
22 bool "Allwinner sun6i internal P2WI controller"
24 If you say yes to this option, support will be included for the
25 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
27 The P2WI looks like an SMBus controller (which supports only byte
28 accesses), except that it only supports one slave device.
29 This interface is used to connect to specific PMIC devices (like the
35 Support for the PRCM (Power/Reset/Clock Management) unit available
39 bool "Sunxi AXP PMIC bus access helpers"
41 Select this PMIC bus access helpers for Sunxi platform PRCM or other
42 AXP family PMIC devices.
45 bool "Allwinner sunXi Reduced Serial Bus Driver"
47 Say y here to enable support for Allwinner's Reduced Serial Bus
48 (RSB) support. This controller is responsible for communicating
49 with various RSB based devices, such as AXP223, AXP8XX PMICs,
52 config SUNXI_HIGH_SRAM
56 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
57 with the first SRAM region being located at address 0.
58 Some newer SoCs map the boot ROM at address 0 instead and move the
59 SRAM to 64KB, just behind the mask ROM.
60 Chips using the latter setup are supposed to select this option to
61 adjust the addresses accordingly.
63 # Note only one of these may be selected at a time! But hidden choices are
64 # not supported by Kconfig
65 config SUNXI_GEN_SUN4I
68 Select this for sunxi SoCs which have resets and clocks set up
69 as the original A10 (mach-sun4i).
71 config SUNXI_GEN_SUN6I
74 Select this for sunxi SoCs which have sun6i like periphery, like
75 separate ahb reset control registers, custom pmic bus, new style
81 Select this for sunxi SoCs which uses a DRAM controller like the
82 DesignWare controller used in H3, mainly SoCs after H3, which do
83 not have official open-source DRAM initialization code, but can
84 use modified H3 DRAM initialization code.
87 config SUNXI_DRAM_DW_16BIT
90 Select this for sunxi SoCs with DesignWare DRAM controller and
91 have only 16-bit memory buswidth.
93 config SUNXI_DRAM_DW_32BIT
96 Select this for sunxi SoCs with DesignWare DRAM controller with
97 32-bit memory buswidth.
100 config MACH_SUNXI_H3_H5
105 select SUNXI_DRAM_DW_32BIT
106 select SUNXI_GEN_SUN6I
110 prompt "Sunxi SoC Variant"
114 bool "sun4i (Allwinner A10)"
116 select ARM_CORTEX_CPU_IS_UP
118 select SUNXI_GEN_SUN4I
122 bool "sun5i (Allwinner A13)"
124 select ARM_CORTEX_CPU_IS_UP
126 select SUNXI_GEN_SUN4I
128 imply CONS_INDEX_2 if !DM_SERIAL
131 bool "sun6i (Allwinner A31)"
133 select CPU_V7_HAS_NONSEC
134 select CPU_V7_HAS_VIRT
135 select ARCH_SUPPORT_PSCI
139 select SUNXI_GEN_SUN6I
141 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
144 bool "sun7i (Allwinner A20)"
146 select CPU_V7_HAS_NONSEC
147 select CPU_V7_HAS_VIRT
148 select ARCH_SUPPORT_PSCI
150 select SUNXI_GEN_SUN4I
152 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
154 config MACH_SUN8I_A23
155 bool "sun8i (Allwinner A23)"
157 select CPU_V7_HAS_NONSEC
158 select CPU_V7_HAS_VIRT
159 select ARCH_SUPPORT_PSCI
160 select SUNXI_GEN_SUN6I
162 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
163 imply CONS_INDEX_5 if !DM_SERIAL
165 config MACH_SUN8I_A33
166 bool "sun8i (Allwinner A33)"
168 select CPU_V7_HAS_NONSEC
169 select CPU_V7_HAS_VIRT
170 select ARCH_SUPPORT_PSCI
171 select SUNXI_GEN_SUN6I
173 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
174 imply CONS_INDEX_5 if !DM_SERIAL
176 config MACH_SUN8I_A83T
177 bool "sun8i (Allwinner A83T)"
179 select SUNXI_GEN_SUN6I
180 select MMC_SUNXI_HAS_NEW_MODE
184 bool "sun8i (Allwinner H3)"
186 select CPU_V7_HAS_NONSEC
187 select CPU_V7_HAS_VIRT
188 select ARCH_SUPPORT_PSCI
189 select MACH_SUNXI_H3_H5
190 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
192 config MACH_SUN8I_R40
193 bool "sun8i (Allwinner R40)"
195 select CPU_V7_HAS_NONSEC
196 select CPU_V7_HAS_VIRT
197 select ARCH_SUPPORT_PSCI
198 select SUNXI_GEN_SUN6I
201 select SUNXI_DRAM_DW_32BIT
203 config MACH_SUN8I_V3S
204 bool "sun8i (Allwinner V3s)"
206 select CPU_V7_HAS_NONSEC
207 select CPU_V7_HAS_VIRT
208 select ARCH_SUPPORT_PSCI
209 select SUNXI_GEN_SUN6I
211 select SUNXI_DRAM_DW_16BIT
213 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
216 bool "sun9i (Allwinner A80)"
219 select SUNXI_HIGH_SRAM
220 select SUNXI_GEN_SUN6I
225 bool "sun50i (Allwinner A64)"
229 select SUNXI_GEN_SUN6I
230 select SUNXI_HIGH_SRAM
233 select SUNXI_DRAM_DW_32BIT
237 config MACH_SUN50I_H5
238 bool "sun50i (Allwinner H5)"
240 select MACH_SUNXI_H3_H5
241 select SUNXI_HIGH_SRAM
247 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
252 default y if MACH_SUN8I_A23
253 default y if MACH_SUN8I_A33
254 default y if MACH_SUN8I_A83T
255 default y if MACH_SUNXI_H3_H5
256 default y if MACH_SUN8I_R40
257 default y if MACH_SUN8I_V3S
259 config RESERVE_ALLWINNER_BOOT0_HEADER
260 bool "reserve space for Allwinner boot0 header"
261 select ENABLE_ARM_SOC_BOOT0_HOOK
263 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
264 filled with magic values post build. The Allwinner provided boot0
265 blob relies on this information to load and execute U-Boot.
266 Only needed on 64-bit Allwinner boards so far when using boot0.
268 config ARM_BOOT_HOOK_RMR
272 select ENABLE_ARM_SOC_BOOT0_HOOK
274 Insert some ARM32 code at the very beginning of the U-Boot binary
275 which uses an RMR register write to bring the core into AArch64 mode.
276 The very first instruction acts as a switch, since it's carefully
277 chosen to be a NOP in one mode and a branch in the other, so the
278 code would only be executed if not already in AArch64.
279 This allows both the SPL and the U-Boot proper to be entered in
280 either mode and switch to AArch64 if needed.
283 config SUNXI_DRAM_DDR3
286 config SUNXI_DRAM_DDR2
289 config SUNXI_DRAM_LPDDR3
293 prompt "DRAM Type and Timing"
294 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
295 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
297 config SUNXI_DRAM_DDR3_1333
299 select SUNXI_DRAM_DDR3
300 depends on !MACH_SUN8I_V3S
302 This option is the original only supported memory type, which suits
303 many H3/H5/A64 boards available now.
305 config SUNXI_DRAM_LPDDR3_STOCK
306 bool "LPDDR3 with Allwinner stock configuration"
307 select SUNXI_DRAM_LPDDR3
309 This option is the LPDDR3 timing used by the stock boot0 by
312 config SUNXI_DRAM_DDR2_V3S
313 bool "DDR2 found in V3s chip"
314 select SUNXI_DRAM_DDR2
315 depends on MACH_SUN8I_V3S
317 This option is only for the DDR2 memory chip which is co-packaged in
324 int "sunxi dram type"
325 depends on MACH_SUN8I_A83T
328 Set the dram type, 3: DDR3, 7: LPDDR3
331 int "sunxi dram clock speed"
332 default 792 if MACH_SUN9I
333 default 648 if MACH_SUN8I_R40
334 default 312 if MACH_SUN6I || MACH_SUN8I
335 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
337 default 672 if MACH_SUN50I
339 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
340 must be a multiple of 24. For the sun9i (A80), the tested values
341 (for DDR3-1600) are 312 to 792.
343 if MACH_SUN5I || MACH_SUN7I
345 int "sunxi mbus clock speed"
348 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
353 int "sunxi dram zq value"
354 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
355 default 127 if MACH_SUN7I
356 default 14779 if MACH_SUN8I_V3S
357 default 3881979 if MACH_SUN8I_R40
358 default 4145117 if MACH_SUN9I
359 default 3881915 if MACH_SUN50I
361 Set the dram zq value.
364 bool "sunxi dram odt enable"
365 default n if !MACH_SUN8I_A23
366 default y if MACH_SUN8I_A23
367 default y if MACH_SUN8I_R40
368 default y if MACH_SUN50I
370 Select this to enable dram odt (on die termination).
372 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
374 int "sunxi dram emr1 value"
375 default 0 if MACH_SUN4I
376 default 4 if MACH_SUN5I || MACH_SUN7I
378 Set the dram controller emr1 value.
381 hex "sunxi dram tpr3 value"
384 Set the dram controller tpr3 parameter. This parameter configures
385 the delay on the command lane and also phase shifts, which are
386 applied for sampling incoming read data. The default value 0
387 means that no phase/delay adjustments are necessary. Properly
388 configuring this parameter increases reliability at high DRAM
391 config DRAM_DQS_GATING_DELAY
392 hex "sunxi dram dqs_gating_delay value"
395 Set the dram controller dqs_gating_delay parmeter. Each byte
396 encodes the DQS gating delay for each byte lane. The delay
397 granularity is 1/4 cycle. For example, the value 0x05060606
398 means that the delay is 5 quarter-cycles for one lane (1.25
399 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
400 The default value 0 means autodetection. The results of hardware
401 autodetection are not very reliable and depend on the chip
402 temperature (sometimes producing different results on cold start
403 and warm reboot). But the accuracy of hardware autodetection
404 is usually good enough, unless running at really high DRAM
405 clocks speeds (up to 600MHz). If unsure, keep as 0.
408 prompt "sunxi dram timings"
409 default DRAM_TIMINGS_VENDOR_MAGIC
411 Select the timings of the DDR3 chips.
413 config DRAM_TIMINGS_VENDOR_MAGIC
414 bool "Magic vendor timings from Android"
416 The same DRAM timings as in the Allwinner boot0 bootloader.
418 config DRAM_TIMINGS_DDR3_1066F_1333H
419 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
421 Use the timings of the standard JEDEC DDR3-1066F speed bin for
422 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
423 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
424 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
425 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
426 that down binning to DDR3-1066F is supported (because DDR3-1066F
427 uses a bit faster timings than DDR3-1333H).
429 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
430 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
432 Use the timings of the slowest possible JEDEC speed bin for the
433 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
434 DDR3-800E, DDR3-1066G or DDR3-1333J.
441 config DRAM_ODT_CORRECTION
442 int "sunxi dram odt correction value"
445 Set the dram odt correction value (range -255 - 255). In allwinner
446 fex files, this option is found in bits 8-15 of the u32 odt_en variable
447 in the [dram] section. When bit 31 of the odt_en variable is set
448 then the correction is negative. Usually the value for this is 0.
452 default 1008000000 if MACH_SUN4I
453 default 1008000000 if MACH_SUN5I
454 default 1008000000 if MACH_SUN6I
455 default 912000000 if MACH_SUN7I
456 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
457 default 1008000000 if MACH_SUN8I
458 default 1008000000 if MACH_SUN9I
460 config SYS_CONFIG_NAME
461 default "sun4i" if MACH_SUN4I
462 default "sun5i" if MACH_SUN5I
463 default "sun6i" if MACH_SUN6I
464 default "sun7i" if MACH_SUN7I
465 default "sun8i" if MACH_SUN8I
466 default "sun9i" if MACH_SUN9I
467 default "sun50i" if MACH_SUN50I
476 bool "UART0 on MicroSD breakout board"
479 Repurpose the SD card slot for getting access to the UART0 serial
480 console. Primarily useful only for low level u-boot debugging on
481 tablets, where normal UART0 is difficult to access and requires
482 device disassembly and/or soldering. As the SD card can't be used
483 at the same time, the system can be only booted in the FEL mode.
484 Only enable this if you really know what you are doing.
486 config OLD_SUNXI_KERNEL_COMPAT
487 bool "Enable workarounds for booting old kernels"
490 Set this to enable various workarounds for old kernels, this results in
491 sub-optimal settings for newer kernels, only enable if needed.
494 string "MAC power pin"
497 Set the pin used to power the MAC. This takes a string in the format
498 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
501 string "Card detect pin for mmc0"
502 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
505 Set the card detect pin for mmc0, leave empty to not use cd. This
506 takes a string in the format understood by sunxi_name_to_gpio, e.g.
507 PH1 for pin 1 of port H.
510 string "Card detect pin for mmc1"
513 See MMC0_CD_PIN help text.
516 string "Card detect pin for mmc2"
519 See MMC0_CD_PIN help text.
522 string "Card detect pin for mmc3"
525 See MMC0_CD_PIN help text.
528 string "Pins for mmc1"
531 Set the pins used for mmc1, when applicable. This takes a string in the
532 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
535 string "Pins for mmc2"
538 See MMC1_PINS help text.
541 string "Pins for mmc3"
544 See MMC1_PINS help text.
546 config MMC_SUNXI_SLOT_EXTRA
547 int "mmc extra slot number"
550 sunxi builds always enable mmc0, some boards also have a second sdcard
551 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
554 config INITIAL_USB_SCAN_DELAY
555 int "delay initial usb scan by x ms to allow builtin devices to init"
558 Some boards have on board usb devices which need longer than the
559 USB spec's 1 second to connect from board powerup. Set this config
560 option to a non 0 value to add an extra delay before the first usb
564 string "Vbus enable pin for usb0 (otg)"
567 Set the Vbus enable pin for usb0 (otg). This takes a string in the
568 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
571 string "Vbus detect pin for usb0 (otg)"
574 Set the Vbus detect pin for usb0 (otg). This takes a string in the
575 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
578 string "ID detect pin for usb0 (otg)"
581 Set the ID detect pin for usb0 (otg). This takes a string in the
582 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
585 string "Vbus enable pin for usb1 (ehci0)"
586 default "PH6" if MACH_SUN4I || MACH_SUN7I
587 default "PH27" if MACH_SUN6I
589 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
590 a string in the format understood by sunxi_name_to_gpio, e.g.
591 PH1 for pin 1 of port H.
594 string "Vbus enable pin for usb2 (ehci1)"
595 default "PH3" if MACH_SUN4I || MACH_SUN7I
596 default "PH24" if MACH_SUN6I
598 See USB1_VBUS_PIN help text.
601 string "Vbus enable pin for usb3 (ehci2)"
604 See USB1_VBUS_PIN help text.
607 bool "Enable I2C/TWI controller 0"
608 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
609 default n if MACH_SUN6I || MACH_SUN8I
612 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
613 its clock and setting up the bus. This is especially useful on devices
614 with slaves connected to the bus or with pins exposed through e.g. an
615 expansion port/header.
618 bool "Enable I2C/TWI controller 1"
622 See I2C0_ENABLE help text.
625 bool "Enable I2C/TWI controller 2"
629 See I2C0_ENABLE help text.
631 if MACH_SUN6I || MACH_SUN7I
633 bool "Enable I2C/TWI controller 3"
637 See I2C0_ENABLE help text.
642 bool "Enable the PRCM I2C/TWI controller"
643 # This is used for the pmic on H3
644 default y if SY8106A_POWER
647 Set this to y to enable the I2C controller which is part of the PRCM.
652 bool "Enable I2C/TWI controller 4"
656 See I2C0_ENABLE help text.
660 bool "Enable support for gpio-s on axp PMICs"
663 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
666 bool "Enable graphical uboot console on HDMI, LCD or VGA"
667 depends on !MACH_SUN8I_A83T
668 depends on !MACH_SUNXI_H3_H5
669 depends on !MACH_SUN8I_R40
670 depends on !MACH_SUN8I_V3S
671 depends on !MACH_SUN9I
672 depends on !MACH_SUN50I
674 imply VIDEO_DT_SIMPLEFB
677 Say Y here to add support for using a cfb console on the HDMI, LCD
678 or VGA output found on most sunxi devices. See doc/README.video for
679 info on how to select the video output and mode.
682 bool "HDMI output support"
683 depends on VIDEO_SUNXI && !MACH_SUN8I
686 Say Y here to add support for outputting video over HDMI.
689 bool "VGA output support"
690 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
693 Say Y here to add support for outputting video over VGA.
695 config VIDEO_VGA_VIA_LCD
696 bool "VGA via LCD controller support"
697 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
700 Say Y here to add support for external DACs connected to the parallel
701 LCD interface driving a VGA connector, such as found on the
704 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
705 bool "Force sync active high for VGA via LCD controller support"
706 depends on VIDEO_VGA_VIA_LCD
709 Say Y here if you've a board which uses opendrain drivers for the vga
710 hsync and vsync signals. Opendrain drivers cannot generate steep enough
711 positive edges for a stable video output, so on boards with opendrain
712 drivers the sync signals must always be active high.
714 config VIDEO_VGA_EXTERNAL_DAC_EN
715 string "LCD panel power enable pin"
716 depends on VIDEO_VGA_VIA_LCD
719 Set the enable pin for the external VGA DAC. This takes a string in the
720 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
722 config VIDEO_COMPOSITE
723 bool "Composite video output support"
724 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
727 Say Y here to add support for outputting composite video.
729 config VIDEO_LCD_MODE
730 string "LCD panel timing details"
731 depends on VIDEO_SUNXI
734 LCD panel timing details string, leave empty if there is no LCD panel.
735 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
736 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
737 Also see: http://linux-sunxi.org/LCD
739 config VIDEO_LCD_DCLK_PHASE
740 int "LCD panel display clock phase"
741 depends on VIDEO_SUNXI || DM_VIDEO
744 Select LCD panel display clock phase shift, range 0-3.
746 config VIDEO_LCD_POWER
747 string "LCD panel power enable pin"
748 depends on VIDEO_SUNXI
751 Set the power enable pin for the LCD panel. This takes a string in the
752 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
754 config VIDEO_LCD_RESET
755 string "LCD panel reset pin"
756 depends on VIDEO_SUNXI
759 Set the reset pin for the LCD panel. This takes a string in the format
760 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
762 config VIDEO_LCD_BL_EN
763 string "LCD panel backlight enable pin"
764 depends on VIDEO_SUNXI
767 Set the backlight enable pin for the LCD panel. This takes a string in the
768 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
771 config VIDEO_LCD_BL_PWM
772 string "LCD panel backlight pwm pin"
773 depends on VIDEO_SUNXI
776 Set the backlight pwm pin for the LCD panel. This takes a string in the
777 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
779 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
780 bool "LCD panel backlight pwm is inverted"
781 depends on VIDEO_SUNXI
784 Set this if the backlight pwm output is active low.
786 config VIDEO_LCD_PANEL_I2C
787 bool "LCD panel needs to be configured via i2c"
788 depends on VIDEO_SUNXI
792 Say y here if the LCD panel needs to be configured via i2c. This
793 will add a bitbang i2c controller using gpios to talk to the LCD.
795 config VIDEO_LCD_PANEL_I2C_SDA
796 string "LCD panel i2c interface SDA pin"
797 depends on VIDEO_LCD_PANEL_I2C
800 Set the SDA pin for the LCD i2c interface. This takes a string in the
801 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
803 config VIDEO_LCD_PANEL_I2C_SCL
804 string "LCD panel i2c interface SCL pin"
805 depends on VIDEO_LCD_PANEL_I2C
808 Set the SCL pin for the LCD i2c interface. This takes a string in the
809 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
812 # Note only one of these may be selected at a time! But hidden choices are
813 # not supported by Kconfig
814 config VIDEO_LCD_IF_PARALLEL
817 config VIDEO_LCD_IF_LVDS
825 bool "Display Engine 2 video driver"
829 imply VIDEO_DT_SIMPLEFB
832 Say y here if you want to build DE2 video driver which is present on
833 newer SoCs. Currently only HDMI output is supported.
837 prompt "LCD panel support"
838 depends on VIDEO_SUNXI
840 Select which type of LCD panel to support.
842 config VIDEO_LCD_PANEL_PARALLEL
843 bool "Generic parallel interface LCD panel"
844 select VIDEO_LCD_IF_PARALLEL
846 config VIDEO_LCD_PANEL_LVDS
847 bool "Generic lvds interface LCD panel"
848 select VIDEO_LCD_IF_LVDS
850 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
851 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
852 select VIDEO_LCD_SSD2828
853 select VIDEO_LCD_IF_PARALLEL
855 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
857 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
858 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
859 select VIDEO_LCD_ANX9804
860 select VIDEO_LCD_IF_PARALLEL
861 select VIDEO_LCD_PANEL_I2C
863 Select this for eDP LCD panels with 4 lanes running at 1.62G,
864 connected via an ANX9804 bridge chip.
866 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
867 bool "Hitachi tx18d42vm LCD panel"
868 select VIDEO_LCD_HITACHI_TX18D42VM
869 select VIDEO_LCD_IF_LVDS
871 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
873 config VIDEO_LCD_TL059WV5C0
874 bool "tl059wv5c0 LCD panel"
875 select VIDEO_LCD_PANEL_I2C
876 select VIDEO_LCD_IF_PARALLEL
878 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
879 Aigo M60/M608/M606 tablets.
884 string "SATA power pin"
887 Set the pins used to power the SATA. This takes a string in the
888 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
892 int "GMAC Transmit Clock Delay Chain"
895 Set the GMAC Transmit Clock Delay Chain value.
897 config SPL_STACK_R_ADDR
898 default 0x4fe00000 if MACH_SUN4I
899 default 0x4fe00000 if MACH_SUN5I
900 default 0x4fe00000 if MACH_SUN6I
901 default 0x4fe00000 if MACH_SUN7I
902 default 0x4fe00000 if MACH_SUN8I
903 default 0x2fe00000 if MACH_SUN9I
904 default 0x4fe00000 if MACH_SUN50I
907 bool "Support for SPI Flash on Allwinner SoCs in SPL"
908 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
910 Enable support for SPI Flash. This option allows SPL to read from
911 sunxi SPI Flash. It uses the same method as the boot ROM, so does
912 not need any extra configuration.