4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
10 bool "Allwinner sun6i internal P2WI controller"
12 If you say yes to this option, support will be included for the
13 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
15 The P2WI looks like an SMBus controller (which supports only byte
16 accesses), except that it only supports one slave device.
17 This interface is used to connect to specific PMIC devices (like the
23 Support for the PRCM (Power/Reset/Clock Management) unit available
26 config SUNXI_HIGH_SRAM
30 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
31 with the first SRAM region being located at address 0.
32 Some newer SoCs map the boot ROM at address 0 instead and move the
33 SRAM to 64KB, just behind the mask ROM.
34 Chips using the latter setup are supposed to select this option to
35 adjust the addresses accordingly.
37 # Note only one of these may be selected at a time! But hidden choices are
38 # not supported by Kconfig
39 config SUNXI_GEN_SUN4I
42 Select this for sunxi SoCs which have resets and clocks set up
43 as the original A10 (mach-sun4i).
45 config SUNXI_GEN_SUN6I
48 Select this for sunxi SoCs which have sun6i like periphery, like
49 separate ahb reset control registers, custom pmic bus, new style
55 Select this for sunxi SoCs which uses a DRAM controller like the
56 DesignWare controller used in H3, mainly SoCs after H3, which do
57 not have official open-source DRAM initialization code, but can
58 use modified H3 DRAM initialization code.
61 config SUNXI_DRAM_DW_16BIT
64 Select this for sunxi SoCs with DesignWare DRAM controller and
65 have only 16-bit memory buswidth.
67 config SUNXI_DRAM_DW_32BIT
70 Select this for sunxi SoCs with DesignWare DRAM controller with
71 32-bit memory buswidth.
74 config MACH_SUNXI_H3_H5
79 select SUNXI_DRAM_DW_32BIT
80 select SUNXI_GEN_SUN6I
84 prompt "Sunxi SoC Variant"
88 bool "sun4i (Allwinner A10)"
90 select ARM_CORTEX_CPU_IS_UP
91 select SUNXI_GEN_SUN4I
95 bool "sun5i (Allwinner A13)"
97 select ARM_CORTEX_CPU_IS_UP
98 select SUNXI_GEN_SUN4I
100 imply CONS_INDEX_2 if !DM_SERIAL
103 bool "sun6i (Allwinner A31)"
105 select CPU_V7_HAS_NONSEC
106 select CPU_V7_HAS_VIRT
107 select ARCH_SUPPORT_PSCI
110 select SUNXI_GEN_SUN6I
112 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
115 bool "sun7i (Allwinner A20)"
117 select CPU_V7_HAS_NONSEC
118 select CPU_V7_HAS_VIRT
119 select ARCH_SUPPORT_PSCI
120 select SUNXI_GEN_SUN4I
122 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
124 config MACH_SUN8I_A23
125 bool "sun8i (Allwinner A23)"
127 select CPU_V7_HAS_NONSEC
128 select CPU_V7_HAS_VIRT
129 select ARCH_SUPPORT_PSCI
130 select SUNXI_GEN_SUN6I
132 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
133 imply CONS_INDEX_5 if !DM_SERIAL
135 config MACH_SUN8I_A33
136 bool "sun8i (Allwinner A33)"
138 select CPU_V7_HAS_NONSEC
139 select CPU_V7_HAS_VIRT
140 select ARCH_SUPPORT_PSCI
141 select SUNXI_GEN_SUN6I
143 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
144 imply CONS_INDEX_5 if !DM_SERIAL
146 config MACH_SUN8I_A83T
147 bool "sun8i (Allwinner A83T)"
149 select SUNXI_GEN_SUN6I
150 select MMC_SUNXI_HAS_NEW_MODE
154 bool "sun8i (Allwinner H3)"
156 select CPU_V7_HAS_NONSEC
157 select CPU_V7_HAS_VIRT
158 select ARCH_SUPPORT_PSCI
159 select MACH_SUNXI_H3_H5
160 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
162 config MACH_SUN8I_R40
163 bool "sun8i (Allwinner R40)"
165 select CPU_V7_HAS_NONSEC
166 select CPU_V7_HAS_VIRT
167 select ARCH_SUPPORT_PSCI
168 select SUNXI_GEN_SUN6I
171 select SUNXI_DRAM_DW_32BIT
173 config MACH_SUN8I_V3S
174 bool "sun8i (Allwinner V3s)"
176 select CPU_V7_HAS_NONSEC
177 select CPU_V7_HAS_VIRT
178 select ARCH_SUPPORT_PSCI
179 select SUNXI_GEN_SUN6I
181 select SUNXI_DRAM_DW_16BIT
183 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
186 bool "sun9i (Allwinner A80)"
188 select SUNXI_HIGH_SRAM
189 select SUNXI_GEN_SUN6I
193 bool "sun50i (Allwinner A64)"
197 select SUNXI_GEN_SUN6I
198 select SUNXI_HIGH_SRAM
201 select SUNXI_DRAM_DW_32BIT
205 config MACH_SUN50I_H5
206 bool "sun50i (Allwinner H5)"
208 select MACH_SUNXI_H3_H5
209 select SUNXI_HIGH_SRAM
215 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
218 default y if MACH_SUN8I_A23
219 default y if MACH_SUN8I_A33
220 default y if MACH_SUN8I_A83T
221 default y if MACH_SUNXI_H3_H5
222 default y if MACH_SUN8I_R40
223 default y if MACH_SUN8I_V3S
225 config RESERVE_ALLWINNER_BOOT0_HEADER
226 bool "reserve space for Allwinner boot0 header"
227 select ENABLE_ARM_SOC_BOOT0_HOOK
229 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
230 filled with magic values post build. The Allwinner provided boot0
231 blob relies on this information to load and execute U-Boot.
232 Only needed on 64-bit Allwinner boards so far when using boot0.
234 config ARM_BOOT_HOOK_RMR
238 select ENABLE_ARM_SOC_BOOT0_HOOK
240 Insert some ARM32 code at the very beginning of the U-Boot binary
241 which uses an RMR register write to bring the core into AArch64 mode.
242 The very first instruction acts as a switch, since it's carefully
243 chosen to be a NOP in one mode and a branch in the other, so the
244 code would only be executed if not already in AArch64.
245 This allows both the SPL and the U-Boot proper to be entered in
246 either mode and switch to AArch64 if needed.
249 config SUNXI_DRAM_DDR3
252 config SUNXI_DRAM_DDR2
255 config SUNXI_DRAM_LPDDR3
259 prompt "DRAM Type and Timing"
260 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
261 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
263 config SUNXI_DRAM_DDR3_1333
265 select SUNXI_DRAM_DDR3
266 depends on !MACH_SUN8I_V3S
268 This option is the original only supported memory type, which suits
269 many H3/H5/A64 boards available now.
271 config SUNXI_DRAM_LPDDR3_STOCK
272 bool "LPDDR3 with Allwinner stock configuration"
273 select SUNXI_DRAM_LPDDR3
275 This option is the LPDDR3 timing used by the stock boot0 by
278 config SUNXI_DRAM_DDR2_V3S
279 bool "DDR2 found in V3s chip"
280 select SUNXI_DRAM_DDR2
281 depends on MACH_SUN8I_V3S
283 This option is only for the DDR2 memory chip which is co-packaged in
290 int "sunxi dram type"
291 depends on MACH_SUN8I_A83T
294 Set the dram type, 3: DDR3, 7: LPDDR3
297 int "sunxi dram clock speed"
298 default 792 if MACH_SUN9I
299 default 648 if MACH_SUN8I_R40
300 default 312 if MACH_SUN6I || MACH_SUN8I
301 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
303 default 672 if MACH_SUN50I
305 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
306 must be a multiple of 24. For the sun9i (A80), the tested values
307 (for DDR3-1600) are 312 to 792.
309 if MACH_SUN5I || MACH_SUN7I
311 int "sunxi mbus clock speed"
314 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
319 int "sunxi dram zq value"
320 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
321 default 127 if MACH_SUN7I
322 default 14779 if MACH_SUN8I_V3S
323 default 3881979 if MACH_SUN8I_R40
324 default 4145117 if MACH_SUN9I
325 default 3881915 if MACH_SUN50I
327 Set the dram zq value.
330 bool "sunxi dram odt enable"
331 default n if !MACH_SUN8I_A23
332 default y if MACH_SUN8I_A23
333 default y if MACH_SUN8I_R40
334 default y if MACH_SUN50I
336 Select this to enable dram odt (on die termination).
338 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
340 int "sunxi dram emr1 value"
341 default 0 if MACH_SUN4I
342 default 4 if MACH_SUN5I || MACH_SUN7I
344 Set the dram controller emr1 value.
347 hex "sunxi dram tpr3 value"
350 Set the dram controller tpr3 parameter. This parameter configures
351 the delay on the command lane and also phase shifts, which are
352 applied for sampling incoming read data. The default value 0
353 means that no phase/delay adjustments are necessary. Properly
354 configuring this parameter increases reliability at high DRAM
357 config DRAM_DQS_GATING_DELAY
358 hex "sunxi dram dqs_gating_delay value"
361 Set the dram controller dqs_gating_delay parmeter. Each byte
362 encodes the DQS gating delay for each byte lane. The delay
363 granularity is 1/4 cycle. For example, the value 0x05060606
364 means that the delay is 5 quarter-cycles for one lane (1.25
365 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
366 The default value 0 means autodetection. The results of hardware
367 autodetection are not very reliable and depend on the chip
368 temperature (sometimes producing different results on cold start
369 and warm reboot). But the accuracy of hardware autodetection
370 is usually good enough, unless running at really high DRAM
371 clocks speeds (up to 600MHz). If unsure, keep as 0.
374 prompt "sunxi dram timings"
375 default DRAM_TIMINGS_VENDOR_MAGIC
377 Select the timings of the DDR3 chips.
379 config DRAM_TIMINGS_VENDOR_MAGIC
380 bool "Magic vendor timings from Android"
382 The same DRAM timings as in the Allwinner boot0 bootloader.
384 config DRAM_TIMINGS_DDR3_1066F_1333H
385 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
387 Use the timings of the standard JEDEC DDR3-1066F speed bin for
388 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
389 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
390 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
391 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
392 that down binning to DDR3-1066F is supported (because DDR3-1066F
393 uses a bit faster timings than DDR3-1333H).
395 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
396 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
398 Use the timings of the slowest possible JEDEC speed bin for the
399 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
400 DDR3-800E, DDR3-1066G or DDR3-1333J.
407 config DRAM_ODT_CORRECTION
408 int "sunxi dram odt correction value"
411 Set the dram odt correction value (range -255 - 255). In allwinner
412 fex files, this option is found in bits 8-15 of the u32 odt_en variable
413 in the [dram] section. When bit 31 of the odt_en variable is set
414 then the correction is negative. Usually the value for this is 0.
418 default 1008000000 if MACH_SUN4I
419 default 1008000000 if MACH_SUN5I
420 default 1008000000 if MACH_SUN6I
421 default 912000000 if MACH_SUN7I
422 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
423 default 1008000000 if MACH_SUN8I
424 default 1008000000 if MACH_SUN9I
426 config SYS_CONFIG_NAME
427 default "sun4i" if MACH_SUN4I
428 default "sun5i" if MACH_SUN5I
429 default "sun6i" if MACH_SUN6I
430 default "sun7i" if MACH_SUN7I
431 default "sun8i" if MACH_SUN8I
432 default "sun9i" if MACH_SUN9I
433 default "sun50i" if MACH_SUN50I
442 bool "UART0 on MicroSD breakout board"
445 Repurpose the SD card slot for getting access to the UART0 serial
446 console. Primarily useful only for low level u-boot debugging on
447 tablets, where normal UART0 is difficult to access and requires
448 device disassembly and/or soldering. As the SD card can't be used
449 at the same time, the system can be only booted in the FEL mode.
450 Only enable this if you really know what you are doing.
452 config OLD_SUNXI_KERNEL_COMPAT
453 bool "Enable workarounds for booting old kernels"
456 Set this to enable various workarounds for old kernels, this results in
457 sub-optimal settings for newer kernels, only enable if needed.
460 string "MAC power pin"
463 Set the pin used to power the MAC. This takes a string in the format
464 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
467 string "Card detect pin for mmc0"
468 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
471 Set the card detect pin for mmc0, leave empty to not use cd. This
472 takes a string in the format understood by sunxi_name_to_gpio, e.g.
473 PH1 for pin 1 of port H.
476 string "Card detect pin for mmc1"
479 See MMC0_CD_PIN help text.
482 string "Card detect pin for mmc2"
485 See MMC0_CD_PIN help text.
488 string "Card detect pin for mmc3"
491 See MMC0_CD_PIN help text.
494 string "Pins for mmc1"
497 Set the pins used for mmc1, when applicable. This takes a string in the
498 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
501 string "Pins for mmc2"
504 See MMC1_PINS help text.
507 string "Pins for mmc3"
510 See MMC1_PINS help text.
512 config MMC_SUNXI_SLOT_EXTRA
513 int "mmc extra slot number"
516 sunxi builds always enable mmc0, some boards also have a second sdcard
517 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
520 config INITIAL_USB_SCAN_DELAY
521 int "delay initial usb scan by x ms to allow builtin devices to init"
524 Some boards have on board usb devices which need longer than the
525 USB spec's 1 second to connect from board powerup. Set this config
526 option to a non 0 value to add an extra delay before the first usb
530 string "Vbus enable pin for usb0 (otg)"
533 Set the Vbus enable pin for usb0 (otg). This takes a string in the
534 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
537 string "Vbus detect pin for usb0 (otg)"
540 Set the Vbus detect pin for usb0 (otg). This takes a string in the
541 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
544 string "ID detect pin for usb0 (otg)"
547 Set the ID detect pin for usb0 (otg). This takes a string in the
548 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
551 string "Vbus enable pin for usb1 (ehci0)"
552 default "PH6" if MACH_SUN4I || MACH_SUN7I
553 default "PH27" if MACH_SUN6I
555 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
556 a string in the format understood by sunxi_name_to_gpio, e.g.
557 PH1 for pin 1 of port H.
560 string "Vbus enable pin for usb2 (ehci1)"
561 default "PH3" if MACH_SUN4I || MACH_SUN7I
562 default "PH24" if MACH_SUN6I
564 See USB1_VBUS_PIN help text.
567 string "Vbus enable pin for usb3 (ehci2)"
570 See USB1_VBUS_PIN help text.
573 bool "Enable I2C/TWI controller 0"
574 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
575 default n if MACH_SUN6I || MACH_SUN8I
578 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
579 its clock and setting up the bus. This is especially useful on devices
580 with slaves connected to the bus or with pins exposed through e.g. an
581 expansion port/header.
584 bool "Enable I2C/TWI controller 1"
588 See I2C0_ENABLE help text.
591 bool "Enable I2C/TWI controller 2"
595 See I2C0_ENABLE help text.
597 if MACH_SUN6I || MACH_SUN7I
599 bool "Enable I2C/TWI controller 3"
603 See I2C0_ENABLE help text.
608 bool "Enable the PRCM I2C/TWI controller"
609 # This is used for the pmic on H3
610 default y if SY8106A_POWER
613 Set this to y to enable the I2C controller which is part of the PRCM.
618 bool "Enable I2C/TWI controller 4"
622 See I2C0_ENABLE help text.
626 bool "Enable support for gpio-s on axp PMICs"
629 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
632 bool "Enable graphical uboot console on HDMI, LCD or VGA"
633 depends on !MACH_SUN8I_A83T
634 depends on !MACH_SUNXI_H3_H5
635 depends on !MACH_SUN8I_R40
636 depends on !MACH_SUN8I_V3S
637 depends on !MACH_SUN9I
638 depends on !MACH_SUN50I
640 imply VIDEO_DT_SIMPLEFB
643 Say Y here to add support for using a cfb console on the HDMI, LCD
644 or VGA output found on most sunxi devices. See doc/README.video for
645 info on how to select the video output and mode.
648 bool "HDMI output support"
649 depends on VIDEO_SUNXI && !MACH_SUN8I
652 Say Y here to add support for outputting video over HDMI.
655 bool "VGA output support"
656 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
659 Say Y here to add support for outputting video over VGA.
661 config VIDEO_VGA_VIA_LCD
662 bool "VGA via LCD controller support"
663 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
666 Say Y here to add support for external DACs connected to the parallel
667 LCD interface driving a VGA connector, such as found on the
670 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
671 bool "Force sync active high for VGA via LCD controller support"
672 depends on VIDEO_VGA_VIA_LCD
675 Say Y here if you've a board which uses opendrain drivers for the vga
676 hsync and vsync signals. Opendrain drivers cannot generate steep enough
677 positive edges for a stable video output, so on boards with opendrain
678 drivers the sync signals must always be active high.
680 config VIDEO_VGA_EXTERNAL_DAC_EN
681 string "LCD panel power enable pin"
682 depends on VIDEO_VGA_VIA_LCD
685 Set the enable pin for the external VGA DAC. This takes a string in the
686 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
688 config VIDEO_COMPOSITE
689 bool "Composite video output support"
690 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
693 Say Y here to add support for outputting composite video.
695 config VIDEO_LCD_MODE
696 string "LCD panel timing details"
697 depends on VIDEO_SUNXI
700 LCD panel timing details string, leave empty if there is no LCD panel.
701 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
702 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
703 Also see: http://linux-sunxi.org/LCD
705 config VIDEO_LCD_DCLK_PHASE
706 int "LCD panel display clock phase"
707 depends on VIDEO_SUNXI || DM_VIDEO
710 Select LCD panel display clock phase shift, range 0-3.
712 config VIDEO_LCD_POWER
713 string "LCD panel power enable pin"
714 depends on VIDEO_SUNXI
717 Set the power enable pin for the LCD panel. This takes a string in the
718 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
720 config VIDEO_LCD_RESET
721 string "LCD panel reset pin"
722 depends on VIDEO_SUNXI
725 Set the reset pin for the LCD panel. This takes a string in the format
726 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
728 config VIDEO_LCD_BL_EN
729 string "LCD panel backlight enable pin"
730 depends on VIDEO_SUNXI
733 Set the backlight enable pin for the LCD panel. This takes a string in the
734 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
737 config VIDEO_LCD_BL_PWM
738 string "LCD panel backlight pwm pin"
739 depends on VIDEO_SUNXI
742 Set the backlight pwm pin for the LCD panel. This takes a string in the
743 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
745 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
746 bool "LCD panel backlight pwm is inverted"
747 depends on VIDEO_SUNXI
750 Set this if the backlight pwm output is active low.
752 config VIDEO_LCD_PANEL_I2C
753 bool "LCD panel needs to be configured via i2c"
754 depends on VIDEO_SUNXI
758 Say y here if the LCD panel needs to be configured via i2c. This
759 will add a bitbang i2c controller using gpios to talk to the LCD.
761 config VIDEO_LCD_PANEL_I2C_SDA
762 string "LCD panel i2c interface SDA pin"
763 depends on VIDEO_LCD_PANEL_I2C
766 Set the SDA pin for the LCD i2c interface. This takes a string in the
767 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
769 config VIDEO_LCD_PANEL_I2C_SCL
770 string "LCD panel i2c interface SCL pin"
771 depends on VIDEO_LCD_PANEL_I2C
774 Set the SCL pin for the LCD i2c interface. This takes a string in the
775 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
778 # Note only one of these may be selected at a time! But hidden choices are
779 # not supported by Kconfig
780 config VIDEO_LCD_IF_PARALLEL
783 config VIDEO_LCD_IF_LVDS
791 bool "Display Engine 2 video driver"
795 imply VIDEO_DT_SIMPLEFB
798 Say y here if you want to build DE2 video driver which is present on
799 newer SoCs. Currently only HDMI output is supported.
803 prompt "LCD panel support"
804 depends on VIDEO_SUNXI
806 Select which type of LCD panel to support.
808 config VIDEO_LCD_PANEL_PARALLEL
809 bool "Generic parallel interface LCD panel"
810 select VIDEO_LCD_IF_PARALLEL
812 config VIDEO_LCD_PANEL_LVDS
813 bool "Generic lvds interface LCD panel"
814 select VIDEO_LCD_IF_LVDS
816 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
817 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
818 select VIDEO_LCD_SSD2828
819 select VIDEO_LCD_IF_PARALLEL
821 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
823 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
824 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
825 select VIDEO_LCD_ANX9804
826 select VIDEO_LCD_IF_PARALLEL
827 select VIDEO_LCD_PANEL_I2C
829 Select this for eDP LCD panels with 4 lanes running at 1.62G,
830 connected via an ANX9804 bridge chip.
832 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
833 bool "Hitachi tx18d42vm LCD panel"
834 select VIDEO_LCD_HITACHI_TX18D42VM
835 select VIDEO_LCD_IF_LVDS
837 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
839 config VIDEO_LCD_TL059WV5C0
840 bool "tl059wv5c0 LCD panel"
841 select VIDEO_LCD_PANEL_I2C
842 select VIDEO_LCD_IF_PARALLEL
844 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
845 Aigo M60/M608/M606 tablets.
850 string "SATA power pin"
853 Set the pins used to power the SATA. This takes a string in the
854 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
858 int "GMAC Transmit Clock Delay Chain"
861 Set the GMAC Transmit Clock Delay Chain value.
863 config SPL_STACK_R_ADDR
864 default 0x4fe00000 if MACH_SUN4I
865 default 0x4fe00000 if MACH_SUN5I
866 default 0x4fe00000 if MACH_SUN6I
867 default 0x4fe00000 if MACH_SUN7I
868 default 0x4fe00000 if MACH_SUN8I
869 default 0x2fe00000 if MACH_SUN9I
870 default 0x4fe00000 if MACH_SUN50I
873 bool "Support for SPI Flash on Allwinner SoCs in SPL"
874 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
876 Enable support for SPI Flash. This option allows SPL to read from
877 sunxi SPI Flash. It uses the same method as the boot ROM, so does
878 not need any extra configuration.